1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# By default dont build CPUs with no FVP model. 35BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 36 37ENABLE_FEAT_AMU := 2 38ENABLE_FEAT_AMUv1p1 := 2 39ENABLE_FEAT_HCX := 2 40ENABLE_FEAT_RNG := 2 41ENABLE_FEAT_TWED := 2 42ENABLE_FEAT_GCS := 2 43 44ifeq (${ARCH}, aarch64) 45 46ifeq (${SPM_MM}, 0) 47ifeq (${CTX_INCLUDE_FPREGS}, 0) 48 ENABLE_SME_FOR_NS := 2 49 ENABLE_SME2_FOR_NS := 2 50else 51 ENABLE_SVE_FOR_NS := 0 52 ENABLE_SME_FOR_NS := 0 53 ENABLE_SME2_FOR_NS := 0 54endif 55endif 56 57 ENABLE_BRBE_FOR_NS := 2 58 ENABLE_TRBE_FOR_NS := 2 59 ENABLE_FEAT_D128 := 2 60endif 61 62ENABLE_SYS_REG_TRACE_FOR_NS := 2 63ENABLE_FEAT_CSV2_2 := 2 64ENABLE_FEAT_CSV2_3 := 2 65ENABLE_FEAT_DEBUGV8P9 := 2 66ENABLE_FEAT_DIT := 2 67ENABLE_FEAT_PAN := 2 68ENABLE_FEAT_VHE := 2 69CTX_INCLUDE_NEVE_REGS := 2 70ENABLE_FEAT_SEL2 := 2 71ENABLE_TRF_FOR_NS := 2 72ENABLE_FEAT_ECV := 2 73ENABLE_FEAT_FGT := 2 74ENABLE_FEAT_FGT2 := 2 75ENABLE_FEAT_THE := 2 76ENABLE_FEAT_TCR2 := 2 77ENABLE_FEAT_S2PIE := 2 78ENABLE_FEAT_S1PIE := 2 79ENABLE_FEAT_S2POE := 2 80ENABLE_FEAT_S1POE := 2 81ENABLE_FEAT_SCTLR2 := 2 82ENABLE_FEAT_MTE2 := 2 83 84# The FVP platform depends on this macro to build with correct GIC driver. 85$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 86 87# Pass FVP_CLUSTER_COUNT to the build system. 88$(eval $(call add_define,FVP_CLUSTER_COUNT)) 89 90# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 91$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 92 93# Pass FVP_MAX_PE_PER_CPU to the build system. 94$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 95 96# Pass FVP_GICR_REGION_PROTECTION to the build system. 97$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 98 99# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 100$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 101 102# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 103# choose the CCI driver , else the CCN driver 104ifeq ($(FVP_CLUSTER_COUNT), 0) 105$(error "Incorrect cluster count specified for FVP port") 106else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 107FVP_INTERCONNECT_DRIVER := FVP_CCI 108else 109FVP_INTERCONNECT_DRIVER := FVP_CCN 110endif 111 112$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 113 114# Choose the GIC sources depending upon the how the FVP will be invoked 115ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 116 117# The GIC model (GIC-600 or GIC-500) will be detected at runtime 118GICV3_SUPPORT_GIC600 := 1 119GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 120 121# Include GICv3 driver files 122include drivers/arm/gic/v3/gicv3.mk 123 124FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 125 plat/common/plat_gicv3.c \ 126 plat/arm/common/arm_gicv3.c 127 128 ifeq ($(filter 1,${RESET_TO_BL2} \ 129 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 130 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 131 endif 132 133else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 134 135# No GICv4 extension 136GIC_ENABLE_V4_EXTN := 0 137$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 138 139# Include GICv2 driver files 140include drivers/arm/gic/v2/gicv2.mk 141 142FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 143 plat/common/plat_gicv2.c \ 144 plat/arm/common/arm_gicv2.c 145 146FVP_DT_PREFIX := fvp-base-gicv2-psci 147else 148$(error "Incorrect GIC driver chosen on FVP port") 149endif 150 151ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 152FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 153else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 154FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 155 plat/arm/common/arm_ccn.c 156else 157$(error "Incorrect CCN driver chosen on FVP port") 158endif 159 160FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 161 plat/arm/board/fvp/fvp_security.c \ 162 plat/arm/common/arm_tzc400.c 163 164 165PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 166 -Iinclude/lib/psa 167 168 169PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 170 171FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 172 173ifeq (${ARCH}, aarch64) 174 175# select a different set of CPU files, depending on whether we compile for 176# hardware assisted coherency cores or not 177ifeq (${HW_ASSISTED_COHERENCY}, 0) 178# Cores used without DSU 179 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 180 lib/cpus/aarch64/cortex_a53.S \ 181 lib/cpus/aarch64/cortex_a57.S \ 182 lib/cpus/aarch64/cortex_a72.S \ 183 lib/cpus/aarch64/cortex_a73.S 184else 185# Cores used with DSU only 186 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 187 # AArch64-only cores 188 # TODO: add all cores to the appropriate lists 189 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 190 lib/cpus/aarch64/cortex_a65ae.S \ 191 lib/cpus/aarch64/cortex_a76.S \ 192 lib/cpus/aarch64/cortex_a76ae.S \ 193 lib/cpus/aarch64/cortex_a77.S \ 194 lib/cpus/aarch64/cortex_a78.S \ 195 lib/cpus/aarch64/cortex_a78_ae.S \ 196 lib/cpus/aarch64/cortex_a78c.S \ 197 lib/cpus/aarch64/cortex_a710.S \ 198 lib/cpus/aarch64/cortex_a715.S \ 199 lib/cpus/aarch64/cortex_a720.S \ 200 lib/cpus/aarch64/cortex_a720_ae.S \ 201 lib/cpus/aarch64/neoverse_n_common.S \ 202 lib/cpus/aarch64/neoverse_n1.S \ 203 lib/cpus/aarch64/neoverse_n2.S \ 204 lib/cpus/aarch64/neoverse_v1.S \ 205 lib/cpus/aarch64/neoverse_e1.S \ 206 lib/cpus/aarch64/cortex_x2.S \ 207 lib/cpus/aarch64/cortex_x4.S 208 endif 209 # AArch64/AArch32 cores 210 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 211 lib/cpus/aarch64/cortex_a75.S 212endif 213 214#Build AArch64-only CPUs with no FVP model yet. 215ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 216 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 217 lib/cpus/aarch64/cortex_gelas.S \ 218 lib/cpus/aarch64/nevis.S \ 219 lib/cpus/aarch64/travis.S \ 220 lib/cpus/aarch64/cortex_arcadia.S 221endif 222 223else 224FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 225 lib/cpus/aarch32/cortex_a57.S \ 226 lib/cpus/aarch32/cortex_a53.S 227endif 228 229BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 230 drivers/arm/sp805/sp805.c \ 231 drivers/delay_timer/delay_timer.c \ 232 drivers/io/io_semihosting.c \ 233 lib/semihosting/semihosting.c \ 234 lib/semihosting/${ARCH}/semihosting_call.S \ 235 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 236 plat/arm/board/fvp/fvp_bl1_setup.c \ 237 plat/arm/board/fvp/fvp_cpu_pwr.c \ 238 plat/arm/board/fvp/fvp_err.c \ 239 plat/arm/board/fvp/fvp_io_storage.c \ 240 plat/arm/board/fvp/fvp_topology.c \ 241 ${FVP_CPU_LIBS} \ 242 ${FVP_INTERCONNECT_SOURCES} 243 244ifeq (${USE_SP804_TIMER},1) 245BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 246else 247BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 248endif 249 250 251BL2_SOURCES += drivers/arm/sp805/sp805.c \ 252 drivers/io/io_semihosting.c \ 253 lib/utils/mem_region.c \ 254 lib/semihosting/semihosting.c \ 255 lib/semihosting/${ARCH}/semihosting_call.S \ 256 plat/arm/board/fvp/fvp_bl2_setup.c \ 257 plat/arm/board/fvp/fvp_err.c \ 258 plat/arm/board/fvp/fvp_io_storage.c \ 259 plat/arm/common/arm_nor_psci_mem_protect.c \ 260 ${FVP_SECURITY_SOURCES} 261 262 263ifeq (${COT_DESC_IN_DTB},1) 264BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 265endif 266 267ifeq (${ENABLE_RME},1) 268BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 269 plat/arm/board/fvp/fvp_cpu_pwr.c 270 271BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 272 plat/arm/board/fvp/fvp_realm_attest_key.c \ 273 plat/arm/board/fvp/fvp_el3_token_sign.c 274endif 275 276ifeq (${ENABLE_FEAT_RNG_TRAP},1) 277BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 278endif 279 280ifeq (${RESET_TO_BL2},1) 281BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 282 plat/arm/board/fvp/fvp_cpu_pwr.c \ 283 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 284 ${FVP_CPU_LIBS} \ 285 ${FVP_INTERCONNECT_SOURCES} 286endif 287 288ifeq (${USE_SP804_TIMER},1) 289BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 290endif 291 292BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 293 ${FVP_SECURITY_SOURCES} 294 295ifeq (${USE_SP804_TIMER},1) 296BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 297endif 298 299BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 300 drivers/arm/smmu/smmu_v3.c \ 301 drivers/delay_timer/delay_timer.c \ 302 drivers/cfi/v2m/v2m_flash.c \ 303 lib/utils/mem_region.c \ 304 plat/arm/board/fvp/fvp_bl31_setup.c \ 305 plat/arm/board/fvp/fvp_console.c \ 306 plat/arm/board/fvp/fvp_pm.c \ 307 plat/arm/board/fvp/fvp_topology.c \ 308 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 309 plat/arm/board/fvp/fvp_cpu_pwr.c \ 310 plat/arm/common/arm_nor_psci_mem_protect.c \ 311 ${FVP_CPU_LIBS} \ 312 ${FVP_GIC_SOURCES} \ 313 ${FVP_INTERCONNECT_SOURCES} \ 314 ${FVP_SECURITY_SOURCES} 315 316# Support for fconf in BL31 317# Added separately from the above list for better readability 318ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 319BL31_SOURCES += lib/fconf/fconf.c \ 320 lib/fconf/fconf_dyn_cfg_getter.c \ 321 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 322 323BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 324 325ifeq (${SEC_INT_DESC_IN_FCONF},1) 326BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 327endif 328 329endif 330 331ifeq (${USE_SP804_TIMER},1) 332BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 333else 334BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 335endif 336 337# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 338ifdef UNIX_MK 339FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 340FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 341 342FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 343$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 344 345ifeq (${TRANSFER_LIST}, 1) 346FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 347 ${PLAT}_tb_fw_config.dts \ 348 ) 349else 350FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 351 ${PLAT}_fw_config.dts \ 352 ${PLAT}_tb_fw_config.dts \ 353 ${PLAT}_soc_fw_config.dts \ 354 ${PLAT}_nt_fw_config.dts \ 355 ) 356 357FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 358FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 359FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 360 361ifeq (${SPD},tspd) 362FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 363FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 364 365# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 366$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 367endif 368 369ifeq (${SPD},spmd) 370 371ifeq ($(ARM_SPMC_MANIFEST_DTS),) 372ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 373endif 374 375FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 376FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 377 378# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 379$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 380endif 381 382# Add the FW_CONFIG to FIP and specify the same to certtool 383$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 384# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 385$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 386# Add the NT_FW_CONFIG to FIP and specify the same to certtool 387$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 388endif 389 390# Add the TB_FW_CONFIG to FIP and specify the same to certtool 391$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 392# Add the HW_CONFIG to FIP and specify the same to certtool 393$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 394endif 395 396ifeq (${TRANSFER_LIST}, 1) 397include lib/transfer_list/transfer_list.mk 398 399ifeq ($(RESET_TO_BL31), 1) 400HW_CONFIG := ${FVP_HW_CONFIG} 401FW_HANDOFF_SIZE := 20000 402 403TRANSFER_LIST_DTB_OFFSET := 0x20 404$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 405endif 406endif 407 408# Enable dynamic mitigation support by default 409DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 410 411ifneq (${ENABLE_FEAT_AMU},0) 412BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 413 lib/cpus/aarch64/cpuamu_helpers.S 414 415ifeq (${HW_ASSISTED_COHERENCY}, 1) 416BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 417 lib/cpus/aarch64/neoverse_n1_pubsub.c 418endif 419endif 420 421ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 422 ifeq (${ENABLE_FEAT_RAS},1) 423 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 424 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 425 else 426 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 427 endif 428 else 429 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 430 endif 431endif 432 433ifneq (${ENABLE_STACK_PROTECTOR},0) 434PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 435endif 436 437# Enable the dynamic translation tables library. 438ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 439 ifeq (${ARCH},aarch32) 440 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 441 else # AArch64 442 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 443 endif 444endif 445 446ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 447 ifeq (${ARCH},aarch32) 448 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 449 else # AArch64 450 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 451 ifeq (${SPD},tspd) 452 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 453 endif 454 endif 455endif 456 457ifeq (${USE_DEBUGFS},1) 458 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 459endif 460 461# Add support for platform supplied linker script for BL31 build 462$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 463 464ifneq (${RESET_TO_BL2}, 0) 465 override BL1_SOURCES = 466endif 467 468include plat/arm/board/common/board_common.mk 469include plat/arm/common/arm_common.mk 470 471ifeq (${MEASURED_BOOT},1) 472BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 473 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 474 lib/psa/measured_boot.c 475 476BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 477 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 478 lib/psa/measured_boot.c 479endif 480 481ifeq (${DRTM_SUPPORT}, 1) 482BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 483 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 484 plat/arm/board/fvp/fvp_drtm_err.c \ 485 plat/arm/board/fvp/fvp_drtm_measurement.c \ 486 plat/arm/board/fvp/fvp_drtm_stub.c \ 487 plat/arm/common/arm_dyn_cfg.c \ 488 plat/arm/board/fvp/fvp_err.c 489endif 490 491ifeq (${TRUSTED_BOARD_BOOT}, 1) 492BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 493BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 494 495# FVP being a development platform, enable capability to disable Authentication 496# dynamically if TRUSTED_BOARD_BOOT is set. 497DYN_DISABLE_AUTH := 1 498endif 499 500ifeq (${SPMC_AT_EL3}, 1) 501PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 502endif 503 504PSCI_OS_INIT_MODE := 1 505 506ifeq (${SPD},spmd) 507BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 508endif 509 510# Test specific macros, keep them at bottom of this file 511$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 512ifeq (${PLATFORM_TEST_EA_FFH}, 1) 513 ifeq (${FFH_SUPPORT}, 0) 514 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 515 endif 516 517endif 518 519$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 520ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 521 ifeq (${ENABLE_FEAT_RAS}, 0) 522 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 523 endif 524 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 525 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 526 endif 527endif 528 529$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 530ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 531 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 532 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 533 endif 534 ifeq (${ENABLE_SPMD_LP}, 0) 535 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 536 endif 537 ifeq (${ENABLE_FEAT_RAS}, 0) 538 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 539 endif 540 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 541 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 542 endif 543endif 544 545ifeq (${ERRATA_ABI_SUPPORT}, 1) 546include plat/arm/board/fvp/fvp_cpu_errata.mk 547endif 548 549# Build macro necessary for running SPM tests on FVP platform 550$(eval $(call add_define,PLAT_TEST_SPM)) 551