1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 35# progbits limit. We need a way to build all useful configurations while waiting 36# on the fvp to increase its SRAM size. The problem is twofild: 37# 1. the cleanup that introduced these enables cleaned up tf-a a little too 38# well and things that previously (incorrectly) were enabled, no longer are. 39# A bunch of CI configs build subtly incorrectly and this combo makes it 40# necessary to forcefully and unconditionally enable them here. 41# 2. the progbits limit is exceeded only when the tsp is involved. However, 42# there are tsp CI configs that run on very high architecture revisions so 43# disabling everything isn't an option. 44# The fix is to enable everything, as before. When the tsp is included, though, 45# we need to slim the size down. In that case, disable all optional features, 46# that will not be present in CI when the tsp is. 47# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 48# for it. 49# TODO: make all of this unconditional (or only base the condition on 50# ARM_ARCH_* when the makefile supports it). 51ifneq (${DRTM_SUPPORT}, 1) 52ifneq (${SPD}, tspd) 53 ENABLE_FEAT_AMU := 2 54 ENABLE_FEAT_AMUv1p1 := 2 55 ENABLE_FEAT_HCX := 2 56 ENABLE_FEAT_RNG := 2 57 ENABLE_FEAT_TWED := 2 58 ENABLE_FEAT_GCS := 2 59ifeq (${ARCH}, aarch64) 60ifeq (${SPM_MM}, 0) 61ifeq (${CTX_INCLUDE_FPREGS}, 0) 62 ENABLE_SME_FOR_NS := 2 63 ENABLE_SME2_FOR_NS := 2 64endif 65endif 66endif 67endif 68 69# enable unconditionally for all builds 70ifeq (${ARCH}, aarch64) 71 ENABLE_BRBE_FOR_NS := 2 72 ENABLE_TRBE_FOR_NS := 2 73endif 74ENABLE_SYS_REG_TRACE_FOR_NS := 2 75ENABLE_FEAT_CSV2_2 := 2 76ENABLE_FEAT_CSV2_3 := 2 77ENABLE_FEAT_DIT := 2 78ENABLE_FEAT_PAN := 2 79ENABLE_FEAT_MTE_PERM := 2 80ENABLE_FEAT_VHE := 2 81CTX_INCLUDE_NEVE_REGS := 2 82ENABLE_FEAT_SEL2 := 2 83ENABLE_TRF_FOR_NS := 2 84ENABLE_FEAT_ECV := 2 85ENABLE_FEAT_FGT := 2 86ENABLE_FEAT_TCR2 := 2 87ENABLE_FEAT_S2PIE := 2 88ENABLE_FEAT_S1PIE := 2 89ENABLE_FEAT_S2POE := 2 90ENABLE_FEAT_S1POE := 2 91endif 92 93# The FVP platform depends on this macro to build with correct GIC driver. 94$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 95 96# Pass FVP_CLUSTER_COUNT to the build system. 97$(eval $(call add_define,FVP_CLUSTER_COUNT)) 98 99# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 100$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 101 102# Pass FVP_MAX_PE_PER_CPU to the build system. 103$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 104 105# Pass FVP_GICR_REGION_PROTECTION to the build system. 106$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 107 108# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 109$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 110 111# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 112# choose the CCI driver , else the CCN driver 113ifeq ($(FVP_CLUSTER_COUNT), 0) 114$(error "Incorrect cluster count specified for FVP port") 115else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 116FVP_INTERCONNECT_DRIVER := FVP_CCI 117else 118FVP_INTERCONNECT_DRIVER := FVP_CCN 119endif 120 121$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 122 123# Choose the GIC sources depending upon the how the FVP will be invoked 124ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 125 126# The GIC model (GIC-600 or GIC-500) will be detected at runtime 127GICV3_SUPPORT_GIC600 := 1 128GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 129 130# Include GICv3 driver files 131include drivers/arm/gic/v3/gicv3.mk 132 133FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 134 plat/common/plat_gicv3.c \ 135 plat/arm/common/arm_gicv3.c 136 137 ifeq ($(filter 1,${RESET_TO_BL2} \ 138 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 139 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 140 endif 141 142else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 143 144# No GICv4 extension 145GIC_ENABLE_V4_EXTN := 0 146$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 147 148# Include GICv2 driver files 149include drivers/arm/gic/v2/gicv2.mk 150 151FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 152 plat/common/plat_gicv2.c \ 153 plat/arm/common/arm_gicv2.c 154 155FVP_DT_PREFIX := fvp-base-gicv2-psci 156else 157$(error "Incorrect GIC driver chosen on FVP port") 158endif 159 160ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 161FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 162else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 163FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 164 plat/arm/common/arm_ccn.c 165else 166$(error "Incorrect CCN driver chosen on FVP port") 167endif 168 169FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 170 plat/arm/board/fvp/fvp_security.c \ 171 plat/arm/common/arm_tzc400.c 172 173 174PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 175 -Iinclude/lib/psa 176 177 178PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 179 180FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 181 182ifeq (${ARCH}, aarch64) 183 184# select a different set of CPU files, depending on whether we compile for 185# hardware assisted coherency cores or not 186ifeq (${HW_ASSISTED_COHERENCY}, 0) 187# Cores used without DSU 188 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 189 lib/cpus/aarch64/cortex_a53.S \ 190 lib/cpus/aarch64/cortex_a57.S \ 191 lib/cpus/aarch64/cortex_a72.S \ 192 lib/cpus/aarch64/cortex_a73.S 193else 194# Cores used with DSU only 195 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 196 # AArch64-only cores 197 # TODO: add all cores to the appropriate lists 198 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 199 lib/cpus/aarch64/cortex_a65ae.S \ 200 lib/cpus/aarch64/cortex_a76.S \ 201 lib/cpus/aarch64/cortex_a76ae.S \ 202 lib/cpus/aarch64/cortex_a77.S \ 203 lib/cpus/aarch64/cortex_a78.S \ 204 lib/cpus/aarch64/cortex_a78_ae.S \ 205 lib/cpus/aarch64/cortex_a78c.S \ 206 lib/cpus/aarch64/cortex_a710.S \ 207 lib/cpus/aarch64/neoverse_n_common.S \ 208 lib/cpus/aarch64/neoverse_n1.S \ 209 lib/cpus/aarch64/neoverse_n2.S \ 210 lib/cpus/aarch64/neoverse_v1.S \ 211 lib/cpus/aarch64/neoverse_e1.S \ 212 lib/cpus/aarch64/cortex_x2.S \ 213 lib/cpus/aarch64/cortex_gelas.S \ 214 lib/cpus/aarch64/nevis.S \ 215 lib/cpus/aarch64/travis.S 216 endif 217 # AArch64/AArch32 cores 218 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 219 lib/cpus/aarch64/cortex_a75.S 220endif 221 222else 223FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 224 lib/cpus/aarch32/cortex_a57.S \ 225 lib/cpus/aarch32/cortex_a53.S 226endif 227 228BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 229 drivers/arm/sp805/sp805.c \ 230 drivers/delay_timer/delay_timer.c \ 231 drivers/io/io_semihosting.c \ 232 lib/semihosting/semihosting.c \ 233 lib/semihosting/${ARCH}/semihosting_call.S \ 234 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 235 plat/arm/board/fvp/fvp_bl1_setup.c \ 236 plat/arm/board/fvp/fvp_err.c \ 237 plat/arm/board/fvp/fvp_io_storage.c \ 238 ${FVP_CPU_LIBS} \ 239 ${FVP_INTERCONNECT_SOURCES} 240 241ifeq (${USE_SP804_TIMER},1) 242BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 243else 244BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 245endif 246 247 248BL2_SOURCES += drivers/arm/sp805/sp805.c \ 249 drivers/io/io_semihosting.c \ 250 lib/utils/mem_region.c \ 251 lib/semihosting/semihosting.c \ 252 lib/semihosting/${ARCH}/semihosting_call.S \ 253 plat/arm/board/fvp/fvp_bl2_setup.c \ 254 plat/arm/board/fvp/fvp_err.c \ 255 plat/arm/board/fvp/fvp_io_storage.c \ 256 plat/arm/common/arm_nor_psci_mem_protect.c \ 257 ${FVP_SECURITY_SOURCES} 258 259 260ifeq (${COT_DESC_IN_DTB},1) 261BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 262endif 263 264ifeq (${ENABLE_RME},1) 265BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 266 267BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 268 plat/arm/board/fvp/fvp_realm_attest_key.c 269endif 270 271ifeq (${ENABLE_FEAT_RNG_TRAP},1) 272BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 273endif 274 275ifeq (${RESET_TO_BL2},1) 276BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 277 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 278 ${FVP_CPU_LIBS} \ 279 ${FVP_INTERCONNECT_SOURCES} 280endif 281 282ifeq (${USE_SP804_TIMER},1) 283BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 284endif 285 286BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 287 ${FVP_SECURITY_SOURCES} 288 289ifeq (${USE_SP804_TIMER},1) 290BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 291endif 292 293BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 294 drivers/arm/smmu/smmu_v3.c \ 295 drivers/delay_timer/delay_timer.c \ 296 drivers/cfi/v2m/v2m_flash.c \ 297 lib/utils/mem_region.c \ 298 plat/arm/board/fvp/fvp_bl31_setup.c \ 299 plat/arm/board/fvp/fvp_console.c \ 300 plat/arm/board/fvp/fvp_pm.c \ 301 plat/arm/board/fvp/fvp_topology.c \ 302 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 303 plat/arm/common/arm_nor_psci_mem_protect.c \ 304 ${FVP_CPU_LIBS} \ 305 ${FVP_GIC_SOURCES} \ 306 ${FVP_INTERCONNECT_SOURCES} \ 307 ${FVP_SECURITY_SOURCES} 308 309# Support for fconf in BL31 310# Added separately from the above list for better readability 311ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 312BL31_SOURCES += lib/fconf/fconf.c \ 313 lib/fconf/fconf_dyn_cfg_getter.c \ 314 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 315 316BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 317 318ifeq (${SEC_INT_DESC_IN_FCONF},1) 319BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 320endif 321 322endif 323 324ifeq (${USE_SP804_TIMER},1) 325BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 326else 327BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 328endif 329 330# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 331ifdef UNIX_MK 332FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 333FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 334 ${PLAT}_fw_config.dts \ 335 ${PLAT}_tb_fw_config.dts \ 336 ${PLAT}_soc_fw_config.dts \ 337 ${PLAT}_nt_fw_config.dts \ 338 ) 339 340FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 341FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 342FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 343FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 344 345ifeq (${SPD},tspd) 346FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 347FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 348 349# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 350$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 351endif 352 353ifeq (${TRANSFER_LIST}, 1) 354include lib/transfer_list/transfer_list.mk 355endif 356 357ifeq (${SPD},spmd) 358 359ifeq ($(ARM_SPMC_MANIFEST_DTS),) 360ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 361endif 362 363FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 364FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 365 366# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 367$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 368endif 369 370# Add the FW_CONFIG to FIP and specify the same to certtool 371$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 372# Add the TB_FW_CONFIG to FIP and specify the same to certtool 373$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 374# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 375$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 376# Add the NT_FW_CONFIG to FIP and specify the same to certtool 377$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 378 379FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 380$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 381 382# Add the HW_CONFIG to FIP and specify the same to certtool 383$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 384endif 385 386# Enable dynamic mitigation support by default 387DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 388 389ifneq (${ENABLE_FEAT_AMU},0) 390BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 391 lib/cpus/aarch64/cpuamu_helpers.S 392 393ifeq (${HW_ASSISTED_COHERENCY}, 1) 394BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 395 lib/cpus/aarch64/neoverse_n1_pubsub.c 396endif 397endif 398 399ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 400 ifeq (${ENABLE_FEAT_RAS},1) 401 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 402 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 403 else 404 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 405 endif 406 else 407 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 408 endif 409endif 410 411ifneq (${ENABLE_STACK_PROTECTOR},0) 412PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 413endif 414 415# Enable the dynamic translation tables library. 416ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 417 ifeq (${ARCH},aarch32) 418 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 419 else # AArch64 420 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 421 endif 422endif 423 424ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 425 ifeq (${ARCH},aarch32) 426 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 427 else # AArch64 428 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 429 ifeq (${SPD},tspd) 430 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 431 endif 432 endif 433endif 434 435ifeq (${USE_DEBUGFS},1) 436 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 437endif 438 439# Add support for platform supplied linker script for BL31 build 440$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 441 442ifneq (${RESET_TO_BL2}, 0) 443 override BL1_SOURCES = 444endif 445 446include plat/arm/board/common/board_common.mk 447include plat/arm/common/arm_common.mk 448 449ifeq (${MEASURED_BOOT},1) 450BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 451 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 452 lib/psa/measured_boot.c 453 454BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 455 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 456 lib/psa/measured_boot.c 457endif 458 459ifeq (${DRTM_SUPPORT}, 1) 460BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 461 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 462 plat/arm/board/fvp/fvp_drtm_err.c \ 463 plat/arm/board/fvp/fvp_drtm_measurement.c \ 464 plat/arm/board/fvp/fvp_drtm_stub.c \ 465 plat/arm/common/arm_dyn_cfg.c \ 466 plat/arm/board/fvp/fvp_err.c 467endif 468 469ifeq (${TRUSTED_BOARD_BOOT}, 1) 470BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 471BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 472 473# FVP being a development platform, enable capability to disable Authentication 474# dynamically if TRUSTED_BOARD_BOOT is set. 475DYN_DISABLE_AUTH := 1 476endif 477 478ifeq (${SPMC_AT_EL3}, 1) 479PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 480endif 481 482PSCI_OS_INIT_MODE := 1 483 484ifeq (${SPD},spmd) 485BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 486endif 487 488# Test specific macros, keep them at bottom of this file 489$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 490ifeq (${PLATFORM_TEST_EA_FFH}, 1) 491 ifeq (${FFH_SUPPORT}, 0) 492 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 493 endif 494 495endif 496 497$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 498ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 499 ifeq (${ENABLE_FEAT_RAS}, 0) 500 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 501 endif 502 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 503 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 504 endif 505endif 506 507$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 508ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 509 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 510 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 511 endif 512 ifeq (${ENABLE_SPMD_LP}, 0) 513 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 514 endif 515 ifeq (${ENABLE_FEAT_RAS}, 0) 516 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 517 endif 518 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 519 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 520 endif 521endif 522 523ifeq (${ERRATA_ABI_SUPPORT}, 1) 524include plat/arm/board/fvp/fvp_cpu_errata.mk 525endif 526 527# Build macro necessary for running SPM tests on FVP platform 528$(eval $(call add_define,PLAT_TEST_SPM)) 529