1# 2# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Use the GICv3 driver on the FVP by default 8FVP_USE_GIC_DRIVER := FVP_GICV3 9 10# Default cluster count for FVP 11FVP_CLUSTER_COUNT := 2 12 13# Default number of CPUs per cluster on FVP 14FVP_MAX_CPUS_PER_CLUSTER := 4 15 16# Default number of threads per CPU on FVP 17FVP_MAX_PE_PER_CPU := 1 18 19FVP_DT_PREFIX := fvp-base-gicv3-psci 20 21# The FVP platform depends on this macro to build with correct GIC driver. 22$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 23 24# Pass FVP_CLUSTER_COUNT to the build system. 25$(eval $(call add_define,FVP_CLUSTER_COUNT)) 26 27# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 28$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 29 30# Pass FVP_MAX_PE_PER_CPU to the build system. 31$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 32 33# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 34# choose the CCI driver , else the CCN driver 35ifeq ($(FVP_CLUSTER_COUNT), 0) 36$(error "Incorrect cluster count specified for FVP port") 37else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 38FVP_INTERCONNECT_DRIVER := FVP_CCI 39else 40FVP_INTERCONNECT_DRIVER := FVP_CCN 41endif 42 43$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 44 45# Choose the GIC sources depending upon the how the FVP will be invoked 46ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 47 48# The GIC model (GIC-600 or GIC-500) will be detected at runtime 49GICV3_SUPPORT_GIC600 := 1 50GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 51 52# Include GICv3 driver files 53include drivers/arm/gic/v3/gicv3.mk 54 55FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 56 plat/common/plat_gicv3.c \ 57 plat/arm/common/arm_gicv3.c 58 59 ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 60 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 61 endif 62 63else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 64 65# No GICv4 extension 66GIC_ENABLE_V4_EXTN := 0 67$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 68 69# Include GICv2 driver files 70include drivers/arm/gic/v2/gicv2.mk 71 72FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 73 plat/common/plat_gicv2.c \ 74 plat/arm/common/arm_gicv2.c 75 76FVP_DT_PREFIX := fvp-base-gicv2-psci 77else 78$(error "Incorrect GIC driver chosen on FVP port") 79endif 80 81ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 82FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 83else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 84FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 85 plat/arm/common/arm_ccn.c 86else 87$(error "Incorrect CCN driver chosen on FVP port") 88endif 89 90FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 91 plat/arm/board/fvp/fvp_security.c \ 92 plat/arm/common/arm_tzc400.c 93 94 95PLAT_INCLUDES := -Iplat/arm/board/fvp/include 96 97 98PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 99 100FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 101 102ifeq (${ARCH}, aarch64) 103 104# select a different set of CPU files, depending on whether we compile for 105# hardware assisted coherency cores or not 106ifeq (${HW_ASSISTED_COHERENCY}, 0) 107# Cores used without DSU 108 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 109 lib/cpus/aarch64/cortex_a53.S \ 110 lib/cpus/aarch64/cortex_a57.S \ 111 lib/cpus/aarch64/cortex_a72.S \ 112 lib/cpus/aarch64/cortex_a73.S 113else 114# Cores used with DSU only 115 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 116 # AArch64-only cores 117 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 118 lib/cpus/aarch64/cortex_a76ae.S \ 119 lib/cpus/aarch64/cortex_a77.S \ 120 lib/cpus/aarch64/cortex_a78.S \ 121 lib/cpus/aarch64/neoverse_n_common.S \ 122 lib/cpus/aarch64/neoverse_n1.S \ 123 lib/cpus/aarch64/neoverse_n2.S \ 124 lib/cpus/aarch64/neoverse_e1.S \ 125 lib/cpus/aarch64/neoverse_v1.S \ 126 lib/cpus/aarch64/cortex_a78_ae.S \ 127 lib/cpus/aarch64/cortex_klein.S \ 128 lib/cpus/aarch64/cortex_matterhorn.S \ 129 lib/cpus/aarch64/cortex_a65.S \ 130 lib/cpus/aarch64/cortex_a65ae.S 131 endif 132 # AArch64/AArch32 cores 133 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 134 lib/cpus/aarch64/cortex_a75.S 135endif 136 137else 138FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S 139endif 140 141BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 142 drivers/arm/sp805/sp805.c \ 143 drivers/delay_timer/delay_timer.c \ 144 drivers/io/io_semihosting.c \ 145 lib/semihosting/semihosting.c \ 146 lib/semihosting/${ARCH}/semihosting_call.S \ 147 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 148 plat/arm/board/fvp/fvp_bl1_setup.c \ 149 plat/arm/board/fvp/fvp_err.c \ 150 plat/arm/board/fvp/fvp_io_storage.c \ 151 ${FVP_CPU_LIBS} \ 152 ${FVP_INTERCONNECT_SOURCES} 153 154ifeq (${USE_SP804_TIMER},1) 155BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 156else 157BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 158endif 159 160 161BL2_SOURCES += drivers/arm/sp805/sp805.c \ 162 drivers/io/io_semihosting.c \ 163 lib/utils/mem_region.c \ 164 lib/semihosting/semihosting.c \ 165 lib/semihosting/${ARCH}/semihosting_call.S \ 166 plat/arm/board/fvp/fvp_bl2_setup.c \ 167 plat/arm/board/fvp/fvp_err.c \ 168 plat/arm/board/fvp/fvp_io_storage.c \ 169 plat/arm/common/arm_nor_psci_mem_protect.c \ 170 ${FVP_SECURITY_SOURCES} 171 172 173ifeq (${COT_DESC_IN_DTB},1) 174BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 175endif 176 177ifeq (${BL2_AT_EL3},1) 178BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 179 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 180 ${FVP_CPU_LIBS} \ 181 ${FVP_INTERCONNECT_SOURCES} 182endif 183 184ifeq (${USE_SP804_TIMER},1) 185BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 186endif 187 188BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 189 ${FVP_SECURITY_SOURCES} 190 191ifeq (${USE_SP804_TIMER},1) 192BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 193endif 194 195BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 196 drivers/arm/smmu/smmu_v3.c \ 197 drivers/delay_timer/delay_timer.c \ 198 drivers/cfi/v2m/v2m_flash.c \ 199 lib/utils/mem_region.c \ 200 plat/arm/board/fvp/fvp_bl31_setup.c \ 201 plat/arm/board/fvp/fvp_console.c \ 202 plat/arm/board/fvp/fvp_pm.c \ 203 plat/arm/board/fvp/fvp_topology.c \ 204 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 205 plat/arm/common/arm_nor_psci_mem_protect.c \ 206 ${FVP_CPU_LIBS} \ 207 ${FVP_GIC_SOURCES} \ 208 ${FVP_INTERCONNECT_SOURCES} \ 209 ${FVP_SECURITY_SOURCES} 210 211# Support for fconf in BL31 212# Added separately from the above list for better readability 213ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31}),) 214BL31_SOURCES += common/fdt_wrappers.c \ 215 lib/fconf/fconf.c \ 216 lib/fconf/fconf_dyn_cfg_getter.c \ 217 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 218 219ifeq (${SEC_INT_DESC_IN_FCONF},1) 220BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 221endif 222 223endif 224 225ifeq (${USE_SP804_TIMER},1) 226BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 227else 228BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 229endif 230 231# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 232ifdef UNIX_MK 233FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 234FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 235 ${PLAT}_fw_config.dts \ 236 ${PLAT}_tb_fw_config.dts \ 237 ${PLAT}_soc_fw_config.dts \ 238 ${PLAT}_nt_fw_config.dts \ 239 ) 240 241FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 242FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 243FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 244FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 245 246ifeq (${SPD},tspd) 247FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 248FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 249 250# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 251$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 252endif 253 254ifeq (${SPD},spmd) 255 256ifeq ($(ARM_SPMC_MANIFEST_DTS),) 257ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 258endif 259 260FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 261FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 262 263# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 264$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 265endif 266 267# Add the FW_CONFIG to FIP and specify the same to certtool 268$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 269# Add the TB_FW_CONFIG to FIP and specify the same to certtool 270$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 271# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 272$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 273# Add the NT_FW_CONFIG to FIP and specify the same to certtool 274$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 275 276FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 277$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 278 279# Add the HW_CONFIG to FIP and specify the same to certtool 280$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 281endif 282 283# Enable Activity Monitor Unit extensions by default 284ENABLE_AMU := 1 285 286# Enable dynamic mitigation support by default 287DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 288 289# Enable reclaiming of BL31 initialisation code for secondary cores 290# stacks for FVP. However, don't enable reclaiming for clang. 291ifneq (${RESET_TO_BL31},1) 292ifeq ($(findstring clang,$(notdir $(CC))),) 293RECLAIM_INIT_CODE := 1 294endif 295endif 296 297ifeq (${ENABLE_AMU},1) 298BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 299 lib/cpus/aarch64/cpuamu_helpers.S 300 301ifeq (${HW_ASSISTED_COHERENCY}, 1) 302BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 303 lib/cpus/aarch64/neoverse_n1_pubsub.c 304endif 305endif 306 307ifeq (${RAS_EXTENSION},1) 308BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 309endif 310 311ifneq (${ENABLE_STACK_PROTECTOR},0) 312PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 313endif 314 315ifeq (${ARCH},aarch32) 316 NEED_BL32 := yes 317endif 318 319# Enable the dynamic translation tables library. 320ifeq (${ARCH},aarch32) 321 ifeq (${RESET_TO_SP_MIN},1) 322 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 323 endif 324else # AArch64 325 ifeq (${RESET_TO_BL31},1) 326 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 327 endif 328 ifeq (${SPD},trusty) 329 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 330 endif 331endif 332 333ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 334 ifeq (${ARCH},aarch32) 335 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 336 else # AArch64 337 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 338 ifeq (${SPD},tspd) 339 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 340 endif 341 endif 342endif 343 344ifeq (${USE_DEBUGFS},1) 345 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 346endif 347 348# Add support for platform supplied linker script for BL31 build 349$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 350 351ifneq (${BL2_AT_EL3}, 0) 352 override BL1_SOURCES = 353endif 354 355include plat/arm/board/common/board_common.mk 356include plat/arm/common/arm_common.mk 357 358ifeq (${TRUSTED_BOARD_BOOT}, 1) 359BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 360BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 361 362ifeq (${MEASURED_BOOT},1) 363BL2_SOURCES += plat/arm/board/fvp/fvp_measured_boot.c 364endif 365 366# FVP being a development platform, enable capability to disable Authentication 367# dynamically if TRUSTED_BOARD_BOOT is set. 368DYN_DISABLE_AUTH := 1 369endif 370