1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2026, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include "def.h" 14 #include <plat_common.h> 15 16 /******************************************************************************* 17 * Generic platform constants 18 ******************************************************************************/ 19 20 /* Size of cacheable stacks */ 21 #ifndef PLATFORM_STACK_SIZE 22 #define PLATFORM_STACK_SIZE U(0x440) 23 #endif 24 25 /* 26 * Variant 14: 1 cluster with 4 cores; 27 * default 42: 4 clusters with 2 cores each. 28 */ 29 #if VERSAL2_VARIANT == 14 30 #define PLATFORM_CLUSTER_COUNT U(1) 31 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) /* 4 CPUs per cluster */ 32 #elif VERSAL2_VARIANT == 42 33 #define PLATFORM_CLUSTER_COUNT U(4) 34 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(2) /* 2 CPUs per cluster */ 35 #else 36 #error "Unsupported VERSAL2_VARIANT. Valid values are 14 or 42." 37 #endif 38 39 /* Power domain descriptor prefix: entry for root + entry for total cluster count */ 40 #define PLAT_PWR_DOMAIN_PREFIX_SIZE U(2) 41 42 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) 43 44 #define E_INVALID_CORE_COUNT -1 45 #define E_INVALID_CLUSTER_COUNT -3 46 47 #define PLAT_MAX_PWR_LVL U(2) 48 #define PLAT_MAX_RET_STATE U(1) 49 #define PLAT_MAX_OFF_STATE U(2) 50 51 /******************************************************************************* 52 * BL31 specific defines. 53 ******************************************************************************/ 54 /* 55 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 56 * present). BL31_BASE is calculated using the current BL31 debug size plus a 57 * little space for growth. 58 */ 59 #ifndef MEM_BASE 60 # define BL31_BASE UL(0xBBF00000) 61 # define BL31_LIMIT UL(0xBC000000) 62 #else 63 # define BL31_BASE UL(MEM_BASE) 64 # define BL31_LIMIT UL(MEM_BASE + MEM_SIZE) 65 # ifdef MEM_PROGBITS_SIZE 66 # define BL31_PROGBITS_LIMIT U(MEM_BASE + \ 67 MEM_PROGBITS_SIZE) 68 # endif 69 #endif 70 71 /******************************************************************************* 72 * BL32 specific defines. 73 ******************************************************************************/ 74 #ifndef BL32_MEM_BASE 75 # define BL32_BASE U(0x01800000) 76 # define BL32_LIMIT U(0x09800000) 77 #else 78 # define BL32_BASE U(BL32_MEM_BASE) 79 # define BL32_LIMIT U(BL32_MEM_BASE + BL32_MEM_SIZE) 80 #endif 81 82 /******************************************************************************* 83 * BL33 specific defines. 84 ******************************************************************************/ 85 #ifndef PRELOADED_BL33_BASE 86 # define PLAT_ARM_NS_IMAGE_BASE U(0x40000000) 87 #else 88 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 89 #endif 90 91 /******************************************************************************* 92 * TSP specific defines. 93 ******************************************************************************/ 94 #define TSP_SEC_MEM_BASE BL32_BASE 95 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 96 97 /* ID of the secure physical generic timer interrupt used by the TSP */ 98 #define ARM_IRQ_SEC_PHY_TIMER U(29) 99 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 100 101 /******************************************************************************* 102 * Platform specific page table and MMU setup constants 103 ******************************************************************************/ 104 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 105 106 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) 107 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) 108 109 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 110 111 #define PLAT_OCM_BASE U(0xBBF00000) 112 #define PLAT_OCM_LIMIT U(0xBC000000) 113 114 #if TRANSFER_LIST 115 /* 116 * FIXME: This address should come from firmware before TF-A 117 * Having this to make sure the transfer list functionality works 118 */ 119 #define FW_HANDOFF_BASE U(0x1000000) 120 #define FW_HANDOFF_SIZE U(0x600000) 121 #endif 122 123 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 124 125 #ifndef MAX_MMAP_REGIONS 126 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 127 #define MAX_MMAP_REGIONS 11 128 #else 129 #define MAX_MMAP_REGIONS 10 130 #endif 131 #endif 132 133 #ifndef MAX_XLAT_TABLES 134 #define MAX_XLAT_TABLES U(12) 135 #endif 136 137 #define CACHE_WRITEBACK_SHIFT U(6) 138 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 139 140 #define PLAT_GICD_BASE_VALUE U(0xE2000000) 141 #define PLAT_GICR_BASE_VALUE U(0xE2060000) 142 #define PLAT_ARM_GICR_BASE PLAT_GICR_BASE_VALUE 143 #define PLAT_ARM_GICD_BASE PLAT_GICD_BASE_VALUE 144 145 /* 146 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 147 * terminology. On a GICv2 system or mode, the lists will be merged and treated 148 * as Group 0 interrupts. 149 */ 150 #define PLAT_IPI_IRQ 89 151 #define PLAT_VERSAL_IPI_IRQ PLAT_IPI_IRQ 152 153 #define PLAT_G1S_IRQ_PROPS(grp) \ 154 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 155 GIC_INTR_CFG_LEVEL) 156 157 #define PLAT_G0_IRQ_PROPS(grp) \ 158 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ 159 GIC_INTR_CFG_EDGE), \ 160 INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, GIC_HIGHEST_SEC_PRIORITY, grp, \ 161 GIC_INTR_CFG_EDGE) 162 163 #define IRQ_MAX 220U 164 165 #endif /* PLATFORM_DEF_H */ 166