1c97857dbSAmit Nagal /* 2c97857dbSAmit Nagal * Copyright (c) 2022, Xilinx, Inc. All rights reserved. 3*e18e67fcSBen Levinsky * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4c97857dbSAmit Nagal * 5c97857dbSAmit Nagal * SPDX-License-Identifier: BSD-3-Clause 6c97857dbSAmit Nagal */ 7c97857dbSAmit Nagal 8c97857dbSAmit Nagal /* Versal Gen 2 IPI management enums and defines */ 9c97857dbSAmit Nagal 10c97857dbSAmit Nagal #ifndef PLAT_IPI_H 11c97857dbSAmit Nagal #define PLAT_IPI_H 12c97857dbSAmit Nagal 13c97857dbSAmit Nagal #include <stdint.h> 14*e18e67fcSBen Levinsky #include <lib/utils_def.h> 15c97857dbSAmit Nagal 16c97857dbSAmit Nagal #include <ipi.h> 17c97857dbSAmit Nagal 18c97857dbSAmit Nagal /********************************************************************* 19c97857dbSAmit Nagal * IPI agent IDs macros 20c97857dbSAmit Nagal ********************************************************************/ 21c97857dbSAmit Nagal #define IPI_ID_PMC 1U 22c97857dbSAmit Nagal #define IPI_ID_APU 2U 23c97857dbSAmit Nagal #define IPI_ID_RPU0 3U 24c97857dbSAmit Nagal #define IPI_ID_RPU1 4U 25c97857dbSAmit Nagal #define IPI_ID_3 5U 26c97857dbSAmit Nagal #define IPI_ID_4 6U 27c97857dbSAmit Nagal #define IPI_ID_5 7U 28c97857dbSAmit Nagal #define IPI_ID_MAX 8U 29c97857dbSAmit Nagal 30c97857dbSAmit Nagal /********************************************************************* 31c97857dbSAmit Nagal * IPI message buffers 32c97857dbSAmit Nagal ********************************************************************/ 33c97857dbSAmit Nagal #define IPI_BUFFER_BASEADDR (0xEB3F0000U) 34c97857dbSAmit Nagal 35c97857dbSAmit Nagal #define IPI_LOCAL_ID IPI_ID_APU 36c97857dbSAmit Nagal #define IPI_REMOTE_ID IPI_ID_PMC 37c97857dbSAmit Nagal 38c97857dbSAmit Nagal #define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + (IPI_LOCAL_ID * 0x200U)) 39c97857dbSAmit Nagal #define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + (IPI_REMOTE_ID * 0x200U)) 40c97857dbSAmit Nagal 41c97857dbSAmit Nagal #define IPI_BUFFER_TARGET_LOCAL_OFFSET (IPI_LOCAL_ID * 0x40U) 42c97857dbSAmit Nagal #define IPI_BUFFER_TARGET_REMOTE_OFFSET (IPI_REMOTE_ID * 0x40U) 43c97857dbSAmit Nagal 44c97857dbSAmit Nagal #define IPI_BUFFER_MAX_WORDS 8 45c97857dbSAmit Nagal 46c97857dbSAmit Nagal #define IPI_BUFFER_REQ_OFFSET 0x0U 47c97857dbSAmit Nagal #define IPI_BUFFER_RESP_OFFSET 0x20U 48c97857dbSAmit Nagal 49c97857dbSAmit Nagal /********************************************************************* 50c97857dbSAmit Nagal * Platform specific IPI API declarations 51c97857dbSAmit Nagal ********************************************************************/ 52c97857dbSAmit Nagal 53c97857dbSAmit Nagal /* Configure IPI table */ 54c97857dbSAmit Nagal extern void soc_ipi_config_table_init(void); 55c97857dbSAmit Nagal 56c97857dbSAmit Nagal /******************************************************************************* 57c97857dbSAmit Nagal * IPI registers and bitfields 58c97857dbSAmit Nagal ******************************************************************************/ 59c97857dbSAmit Nagal #define IPI0_REG_BASE (0xEB330000U) 60*e18e67fcSBen Levinsky #define IPI0_TRIG_BIT BIT_32(2) 61*e18e67fcSBen Levinsky #define PMC_IPI_TRIG_BIT BIT_32(1) 62c97857dbSAmit Nagal #define IPI1_REG_BASE (0xEB340000U) 63*e18e67fcSBen Levinsky #define IPI1_TRIG_BIT BIT_32(3) 64c97857dbSAmit Nagal #define IPI2_REG_BASE (0xEB350000U) 65*e18e67fcSBen Levinsky #define IPI2_TRIG_BIT BIT_32(4) 66c97857dbSAmit Nagal #define IPI3_REG_BASE (0xEB360000U) 67*e18e67fcSBen Levinsky #define IPI3_TRIG_BIT BIT_32(5) 68c97857dbSAmit Nagal #define IPI4_REG_BASE (0xEB370000U) 69*e18e67fcSBen Levinsky #define IPI4_TRIG_BIT BIT_32(6) 70c97857dbSAmit Nagal #define IPI5_REG_BASE (0xEB380000U) 71*e18e67fcSBen Levinsky #define IPI5_TRIG_BIT BIT_32(7) 72c97857dbSAmit Nagal 73c97857dbSAmit Nagal #endif /* PLAT_IPI_H */ 74