1*c97857dbSAmit Nagal /* 2*c97857dbSAmit Nagal * Copyright (c) 2022, Xilinx, Inc. All rights reserved. 3*c97857dbSAmit Nagal * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 4*c97857dbSAmit Nagal * 5*c97857dbSAmit Nagal * SPDX-License-Identifier: BSD-3-Clause 6*c97857dbSAmit Nagal */ 7*c97857dbSAmit Nagal 8*c97857dbSAmit Nagal /* Versal Gen 2 IPI management enums and defines */ 9*c97857dbSAmit Nagal 10*c97857dbSAmit Nagal #ifndef PLAT_IPI_H 11*c97857dbSAmit Nagal #define PLAT_IPI_H 12*c97857dbSAmit Nagal 13*c97857dbSAmit Nagal #include <stdint.h> 14*c97857dbSAmit Nagal 15*c97857dbSAmit Nagal #include <ipi.h> 16*c97857dbSAmit Nagal 17*c97857dbSAmit Nagal /********************************************************************* 18*c97857dbSAmit Nagal * IPI agent IDs macros 19*c97857dbSAmit Nagal ********************************************************************/ 20*c97857dbSAmit Nagal #define IPI_ID_PMC 1U 21*c97857dbSAmit Nagal #define IPI_ID_APU 2U 22*c97857dbSAmit Nagal #define IPI_ID_RPU0 3U 23*c97857dbSAmit Nagal #define IPI_ID_RPU1 4U 24*c97857dbSAmit Nagal #define IPI_ID_3 5U 25*c97857dbSAmit Nagal #define IPI_ID_4 6U 26*c97857dbSAmit Nagal #define IPI_ID_5 7U 27*c97857dbSAmit Nagal #define IPI_ID_MAX 8U 28*c97857dbSAmit Nagal 29*c97857dbSAmit Nagal /********************************************************************* 30*c97857dbSAmit Nagal * IPI message buffers 31*c97857dbSAmit Nagal ********************************************************************/ 32*c97857dbSAmit Nagal #define IPI_BUFFER_BASEADDR (0xEB3F0000U) 33*c97857dbSAmit Nagal 34*c97857dbSAmit Nagal #define IPI_LOCAL_ID IPI_ID_APU 35*c97857dbSAmit Nagal #define IPI_REMOTE_ID IPI_ID_PMC 36*c97857dbSAmit Nagal 37*c97857dbSAmit Nagal #define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + (IPI_LOCAL_ID * 0x200U)) 38*c97857dbSAmit Nagal #define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + (IPI_REMOTE_ID * 0x200U)) 39*c97857dbSAmit Nagal 40*c97857dbSAmit Nagal #define IPI_BUFFER_TARGET_LOCAL_OFFSET (IPI_LOCAL_ID * 0x40U) 41*c97857dbSAmit Nagal #define IPI_BUFFER_TARGET_REMOTE_OFFSET (IPI_REMOTE_ID * 0x40U) 42*c97857dbSAmit Nagal 43*c97857dbSAmit Nagal #define IPI_BUFFER_MAX_WORDS 8 44*c97857dbSAmit Nagal 45*c97857dbSAmit Nagal #define IPI_BUFFER_REQ_OFFSET 0x0U 46*c97857dbSAmit Nagal #define IPI_BUFFER_RESP_OFFSET 0x20U 47*c97857dbSAmit Nagal 48*c97857dbSAmit Nagal /********************************************************************* 49*c97857dbSAmit Nagal * Platform specific IPI API declarations 50*c97857dbSAmit Nagal ********************************************************************/ 51*c97857dbSAmit Nagal 52*c97857dbSAmit Nagal /* Configure IPI table */ 53*c97857dbSAmit Nagal extern void soc_ipi_config_table_init(void); 54*c97857dbSAmit Nagal 55*c97857dbSAmit Nagal /******************************************************************************* 56*c97857dbSAmit Nagal * IPI registers and bitfields 57*c97857dbSAmit Nagal ******************************************************************************/ 58*c97857dbSAmit Nagal #define IPI0_REG_BASE (0xEB330000U) 59*c97857dbSAmit Nagal #define IPI0_TRIG_BIT (1 << 2) 60*c97857dbSAmit Nagal #define PMC_IPI_TRIG_BIT (1 << 1) 61*c97857dbSAmit Nagal #define IPI1_REG_BASE (0xEB340000U) 62*c97857dbSAmit Nagal #define IPI1_TRIG_BIT (1 << 3) 63*c97857dbSAmit Nagal #define IPI2_REG_BASE (0xEB350000U) 64*c97857dbSAmit Nagal #define IPI2_TRIG_BIT (1 << 4) 65*c97857dbSAmit Nagal #define IPI3_REG_BASE (0xEB360000U) 66*c97857dbSAmit Nagal #define IPI3_TRIG_BIT (1 << 5) 67*c97857dbSAmit Nagal #define IPI4_REG_BASE (0xEB370000U) 68*c97857dbSAmit Nagal #define IPI4_TRIG_BIT (1 << 6) 69*c97857dbSAmit Nagal #define IPI5_REG_BASE (0xEB380000U) 70*c97857dbSAmit Nagal #define IPI5_TRIG_BIT (1 << 7) 71*c97857dbSAmit Nagal 72*c97857dbSAmit Nagal #endif /* PLAT_IPI_H */ 73