1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <platform_def.h> 12 13#define LIT_CAPACITY 239 14#define MID_CAPACITY 686 15#define BIG_CAPACITY 1024 16 17#define MHU_TX_ADDR 46040000 /* hex */ 18#define MHU_TX_COMPAT "arm,mhuv3" 19#define MHU_TX_INT_NAME "" 20 21#define MHU_RX_ADDR 46140000 /* hex */ 22#define MHU_RX_COMPAT "arm,mhuv3" 23#define MHU_OFFSET 0x10000 24#define MHU_MBOX_CELLS 3 25#define MHU_RX_INT_NUM 300 26#define MHU_RX_INT_NAME "combined-mbx" 27 28#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ 29#define UARTCLK_FREQ 3750000 30 31#if TARGET_FLAVOUR_FVP 32#define DPU_ADDR 4000000000 33#define DPU_IRQ 579 34#elif TARGET_FLAVOUR_FPGA 35#define DPU_ADDR 2cc00000 36#define DPU_IRQ 69 37#endif 38 39#include "tc-common.dtsi" 40#if TARGET_FLAVOUR_FVP 41#include "tc-fvp.dtsi" 42#else 43#include "tc-fpga.dtsi" 44#endif /* TARGET_FLAVOUR_FVP */ 45#include "tc-base.dtsi" 46 47/ { 48 cpus { 49 CPU2:cpu@200 { 50 clocks = <&scmi_dvfs 1>; 51 capacity-dmips-mhz = <MID_CAPACITY>; 52 }; 53 54 CPU3:cpu@300 { 55 clocks = <&scmi_dvfs 1>; 56 capacity-dmips-mhz = <MID_CAPACITY>; 57 }; 58 59 CPU6:cpu@600 { 60 clocks = <&scmi_dvfs 2>; 61 capacity-dmips-mhz = <BIG_CAPACITY>; 62 }; 63 64 CPU7:cpu@700 { 65 clocks = <&scmi_dvfs 2>; 66 capacity-dmips-mhz = <BIG_CAPACITY>; 67 }; 68 }; 69 70 cpu-pmu { 71 interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, 72 <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; 73 }; 74 75 cs-pmu@0 { 76 compatible = "arm,coresight-pmu"; 77 reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>; 78 }; 79 80 cs-pmu@1 { 81 compatible = "arm,coresight-pmu"; 82 reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>; 83 }; 84 85 cs-pmu@2 { 86 compatible = "arm,coresight-pmu"; 87 reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>; 88 }; 89 90 cs-pmu@3 { 91 compatible = "arm,coresight-pmu"; 92 reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>; 93 }; 94 95 dsu-pmu { 96 compatible = "arm,dsu-pmu"; 97 cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; 98 }; 99 100 sram: sram@6000000 { 101 cpu_scp_scmi_p2a: scp-shmem@80 { 102 compatible = "arm,scmi-shmem"; 103 reg = <0x80 0x80>; 104 }; 105 }; 106 107 firmware { 108 scmi { 109 mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>; 110 shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>; 111 }; 112 }; 113 114#if TARGET_FLAVOUR_FVP 115 smmu_700: iommu@3f000000 { 116 status = "okay"; 117 }; 118 119 smmu_700_dpu: iommu@4002a00000 { 120 status = "okay"; 121 }; 122#else 123 smmu_600: smmu@2ce00000 { 124 status = "okay"; 125 }; 126#endif 127 128 dp0: display@DPU_ADDR { 129#if TARGET_FLAVOUR_FVP 130 iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, 131 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; 132#else /* TARGET_FLAVOUR_FPGA */ 133 iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>, 134 <&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>, 135 <&smmu_600 8>, <&smmu_600 9>; 136#endif 137 }; 138 139 gpu: gpu@2d000000 { 140#if TARGET_FLAVOUR_FVP 141 iommus = <&smmu_700 0x200>; 142#endif 143 }; 144}; 145