1b3a9737cSLeo Yan/* 2b3a9737cSLeo Yan * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3b3a9737cSLeo Yan * 4b3a9737cSLeo Yan * SPDX-License-Identifier: BSD-3-Clause 5b3a9737cSLeo Yan */ 6b3a9737cSLeo Yan 7b3a9737cSLeo Yan/dts-v1/; 8b3a9737cSLeo Yan 9b3a9737cSLeo Yan#include <dt-bindings/interrupt-controller/arm-gic.h> 10b3a9737cSLeo Yan#include <dt-bindings/interrupt-controller/irq.h> 11b3a9737cSLeo Yan#include <platform_def.h> 12b3a9737cSLeo Yan 13*defcfb2bSLeo Yan#define LIT_CAPACITY 239 14*defcfb2bSLeo Yan#define MID_CAPACITY 686 15*defcfb2bSLeo Yan#define BIG_CAPACITY 1024 16*defcfb2bSLeo Yan 17*defcfb2bSLeo Yan#define INT_MBOX_RX 300 18*defcfb2bSLeo Yan#define MHU_TX_ADDR 46040000 /* hex */ 19*defcfb2bSLeo Yan#define MHU_RX_ADDR 46140000 /* hex */ 20*defcfb2bSLeo Yan#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ 21*defcfb2bSLeo Yan#define UARTCLK_FREQ 3750000 22*defcfb2bSLeo Yan 23*defcfb2bSLeo Yan#if TARGET_FLAVOUR_FVP 24*defcfb2bSLeo Yan#define DPU_ADDR 4000000000 25*defcfb2bSLeo Yan#define DPU_IRQ 579 26*defcfb2bSLeo Yan#elif TARGET_FLAVOUR_FPGA 27*defcfb2bSLeo Yan#define DPU_ADDR 2cc00000 28*defcfb2bSLeo Yan#define DPU_IRQ 69 29*defcfb2bSLeo Yan#endif 30*defcfb2bSLeo Yan 31b3a9737cSLeo Yan#include "tc-common.dtsi" 32b3a9737cSLeo Yan#if TARGET_FLAVOUR_FVP 33b3a9737cSLeo Yan#include "tc-fvp.dtsi" 34b3a9737cSLeo Yan#endif /* TARGET_FLAVOUR_FVP */ 35b3a9737cSLeo Yan#include "tc-base.dtsi" 36