/* * Copyright (c) 2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /dts-v1/; #include / { model = "RD-Aspen"; compatible = "arm,rdaspen"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; chosen { stdout-path = &soc_serial0; }; cpus { #address-cells = <2>; #size-cells = <0>; /* 4 clusters and 4 CPU cores in each cluster */ cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; CL0_L3: l3-cache0 { compatible = "arm,dsu-l3-cache", "cache"; cache-level = <0x03>; /* 4MB */ cache-size = <0x400000>; /* 64B */ cache-line-size = <0x40>; /* 16-way set */ cache-sets = <0x1000>; }; }; cluster1 { core0 { cpu = <&CPU4>; }; core1 { cpu = <&CPU5>; }; core2 { cpu = <&CPU6>; }; core3 { cpu = <&CPU7>; }; CL1_L3: l3-cache1 { compatible = "arm,dsu-l3-cache", "cache"; cache-level = <0x03>; /* 4MB */ cache-size = <0x400000>; /* 64B */ cache-line-size = <0x40>; /* 16-way set */ cache-sets = <0x1000>; }; }; cluster2 { core0 { cpu = <&CPU8>; }; core1 { cpu = <&CPU9>; }; core2 { cpu = <&CPU10>; }; core3 { cpu = <&CPU11>; }; CL2_L3: l3-cache2 { compatible = "arm,dsu-l3-cache", "cache"; cache-level = <0x03>; /* 4MB */ cache-size = <0x400000>; /* 64B */ cache-line-size = <0x40>; /* 16-way set */ cache-sets = <0x1000>; }; }; cluster3 { core0 { cpu = <&CPU12>; }; core1 { cpu = <&CPU13>; }; core2 { cpu = <&CPU14>; }; core3 { cpu = <&CPU15>; }; CL3_L3: l3-cache3 { compatible = "arm,dsu-l3-cache", "cache"; cache-level = <0x03>; /* 4MB */ cache-size = <0x400000>; /* 64B */ cache-line-size = <0x40>; /* 16-way set */ cache-sets = <0x1000>; }; }; }; CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x0>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL0_L2_0>; CL0_L2_0: l2-cache0 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL0_L3>; }; }; CPU1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x100>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL0_L2_1>; CL0_L2_1: l2-cache1 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL0_L3>; }; }; CPU2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x200>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL0_L2_2>; CL0_L2_2: l2-cache2 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL0_L3>; }; }; CPU3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x300>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL0_L2_3>; CL0_L2_3: l2-cache3 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL0_L3>; }; }; CPU4: cpu@10000 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x10000>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL1_L2_0>; CL1_L2_0: l2-cache4 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL1_L3>; }; }; CPU5: cpu@10100 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x10100>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL1_L2_1>; CL1_L2_1: l2-cache5 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL1_L3>; }; }; CPU6: cpu@10200 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x10200>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL1_L2_2>; CL1_L2_2: l2-cache6 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL1_L3>; }; }; CPU7: cpu@10300 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x10300>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL1_L2_3>; CL1_L2_3: l2-cache7 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL1_L3>; }; }; CPU8: cpu@20000 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x20000>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL2_L2_0>; CL2_L2_0: l2-cache8 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL2_L3>; }; }; CPU9: cpu@20100 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x20100>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL2_L2_1>; CL2_L2_1: l2-cache9 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL2_L3>; }; }; CPU10: cpu@20200 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x20200>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL2_L2_2>; CL2_L2_2: l2-cache10 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL2_L3>; }; }; CPU11: cpu@20300 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x20300>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL2_L2_3>; CL2_L2_3: l2-cache11 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL2_L3>; }; }; CPU12: cpu@30000 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x30000>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL3_L2_0>; CL3_L2_0: l2-cache12 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL3_L3>; }; }; CPU13: cpu@30100 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x30100>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL3_L2_1>; CL3_L2_1: l2-cache13 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL3_L3>; }; }; CPU14: cpu@30200 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x30200>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL3_L2_2>; CL3_L2_2: l2-cache14 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL3_L3>; }; }; CPU15: cpu@30300 { device_type = "cpu"; compatible = "arm,cortex-a720ae"; reg = <0x0 0x30300>; enable-method = "psci"; i-cache-size = <0x10000>; i-cache-line-size = <0x40>; i-cache-sets = <0x100>; d-cache-size = <0x10000>; d-cache-line-size = <0x40>; d-cache-sets = <0x100>; next-level-cache = <&CL3_L2_3>; CL3_L2_3: l2-cache15 { compatible = "cache"; cache-level = <0x02>; /* 512KB */ cache-size = <0x80000>; /* 64B */ cache-line-size = <0x40>; /* 8-way set */ cache-sets = <0x400>; next-level-cache = <&CL3_L3>; }; }; }; dsu-pmu-0 { compatible = "arm,dsu-pmu"; cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>; interrupts = ; }; dsu-pmu-1 { compatible = "arm,dsu-pmu"; cpus = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; interrupts = ; }; dsu-pmu-2 { compatible = "arm,dsu-pmu"; cpus = <&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>; interrupts = ; }; dsu-pmu-3 { compatible = "arm,dsu-pmu"; cpus = <&CPU12>, <&CPU13>, <&CPU14>, <&CPU15>; interrupts = ; }; memory@80000000 { device_type = "memory"; /* Bank 0: start = 0x0000_0000_8000_0000, size = ~2 GiB (0x7F00_0000) */ /* Bank 1: start = 0x0000_0200_0000_0000, size = 2 GiB (0x8000_0000) */ reg = < 0x00000000 0x80000000 0x00000000 0x7F000000 0x00000200 0x00000000 0x00000000 0x80000000 >; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , , ; }; soc_clk24mhz: clk24mhz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "refclk24mhz"; }; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; timer@1a810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x1a810000 0 0x10000>; #address-cells = <1>; #size-cells = <1>; /* Map child space [0x0..0x30000) to parent @ 0x1a810000 */ ranges = <0x0 0x0 0x1a810000 0x00030000>; frame@20000 { frame-number = <1>; interrupts = ; reg = <0x20000 0x10000>; }; }; gic: interrupt-controller@20000000 { compatible = "arm,gic-v3"; reg = <0x0 0x20000000 0x0 0x10000>, /* GICD */ <0x0 0x200c0000 0x0 0x400000>; /* 16 * GICR */ #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-controller; interrupts = ; its1: msi-controller@20040000 { compatible = "arm,gic-v3-its"; reg = <0x0 0x20040000 0x0 0x40000>; msi-controller; #msi-cells = <1>; }; its2: msi-controller@20080000 { compatible = "arm,gic-v3-its"; reg = <0x0 0x20080000 0x0 0x40000>; msi-controller; #msi-cells = <1>; }; }; /* UART is fixed as 24MHz, both UARTCLK and PCLK */ soc_serial0: serial@1a400000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x1a400000 0x0 0x10000>; interrupts = ; clocks = <&soc_clk24mhz>, <&soc_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; watchdog@1a420000 { compatible = "arm,sbsa-gwdt"; reg = <0x0 0x1a420000 0x0 0x10000>, <0x0 0x1a430000 0x0 0x10000>; interrupts = ; }; rtc@300d0000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x0 0x300d0000 0x0 0x10000>; interrupts = ; clocks = <&soc_clk24mhz>; clock-names = "apb_pclk"; }; virtio-net@30060000 { compatible = "virtio,mmio"; reg = <0x0 0x30060000 0x0 0x10000>; interrupts = ; }; /* OS storage */ virtio-block@30020000 { compatible = "virtio,mmio"; reg = <0x0 0x30020000 0x0 0x10000>; interrupts = ; }; /* Distro installation media */ virtio-block@30030000 { compatible = "virtio,mmio"; reg = <0x0 0x30030000 0x0 0x10000>; interrupts = ; }; /* SystemReady ACS validation media */ virtio-block@30040000 { compatible = "virtio,mmio"; reg = <0x0 0x30040000 0x0 0x10000>; interrupts = ; }; /* User data media */ virtio-block@30050000 { compatible = "virtio,mmio"; reg = <0x0 0x30050000 0x0 0x10000>; interrupts = ; }; virtio-rng@30080000 { compatible = "virtio,mmio"; reg = <0x0 0x30080000 0x0 0x10000>; interrupts = ; }; }; psci { compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; method = "smc"; cpu_suspend = <0xc4000001>; cpu_off = <0x84000002>; cpu_on = <0xc4000003>; }; };