1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* CP110 Marvell SoC driver */ 9 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <drivers/marvell/amb_adec.h> 13 #include <drivers/marvell/iob.h> 14 #include <drivers/marvell/mochi/cp110_setup.h> 15 16 #include <plat_marvell.h> 17 18 /* 19 * AXI Configuration. 20 */ 21 22 /* Used for Units of CP-110 (e.g. USB device, USB Host, and etc) */ 23 #define MVEBU_AXI_ATTR_OFFSET (0x441300) 24 #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_OFFSET + \ 25 0x4 * index) 26 27 /* AXI Protection bits */ 28 #define MVEBU_AXI_PROT_OFFSET (0x441200) 29 30 /* AXI Protection regs */ 31 #define MVEBU_AXI_PROT_REG(index) ((index <= 4) ? \ 32 (MVEBU_AXI_PROT_OFFSET + \ 33 0x4 * index) : \ 34 (MVEBU_AXI_PROT_OFFSET + 0x18)) 35 #define MVEBU_AXI_PROT_REGS_NUM (6) 36 37 #define MVEBU_SOC_CFGS_OFFSET (0x441900) 38 #define MVEBU_SOC_CFG_REG(index) (MVEBU_SOC_CFGS_OFFSET + \ 39 0x4 * index) 40 #define MVEBU_SOC_CFG_REG_NUM (0) 41 #define MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK (0xE) 42 43 /* SATA3 MBUS to AXI regs */ 44 #define MVEBU_BRIDGE_WIN_DIS_REG (MVEBU_SOC_CFGS_OFFSET + 0x10) 45 #define MVEBU_BRIDGE_WIN_DIS_OFF (0x0) 46 47 /* SATA3 MBUS to AXI regs */ 48 #define MVEBU_SATA_M2A_AXI_PORT_CTRL_REG (0x54ff04) 49 50 /* AXI to MBUS bridge registers */ 51 #define MVEBU_AMB_IP_OFFSET (0x13ff00) 52 #define MVEBU_AMB_IP_BRIDGE_WIN_REG(win) (MVEBU_AMB_IP_OFFSET + \ 53 (win * 0x8)) 54 #define MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET 0 55 #define MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK \ 56 (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET) 57 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET 16 58 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK \ 59 (0xffffu << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) 60 61 #define MVEBU_SAMPLE_AT_RESET_REG (0x440600) 62 #define SAR_PCIE1_CLK_CFG_OFFSET 31 63 #define SAR_PCIE1_CLK_CFG_MASK (0x1u << SAR_PCIE1_CLK_CFG_OFFSET) 64 #define SAR_PCIE0_CLK_CFG_OFFSET 30 65 #define SAR_PCIE0_CLK_CFG_MASK (0x1 << SAR_PCIE0_CLK_CFG_OFFSET) 66 #define SAR_I2C_INIT_EN_OFFSET 24 67 #define SAR_I2C_INIT_EN_MASK (1 << SAR_I2C_INIT_EN_OFFSET) 68 69 /******************************************************************************* 70 * PCIE clock buffer control 71 ******************************************************************************/ 72 #define MVEBU_PCIE_REF_CLK_BUF_CTRL (0x4404F0) 73 #define PCIE1_REFCLK_BUFF_SOURCE 0x800 74 #define PCIE0_REFCLK_BUFF_SOURCE 0x400 75 76 /******************************************************************************* 77 * MSS Device Push Set Register 78 ******************************************************************************/ 79 #define MVEBU_CP_MSS_DPSHSR_REG (0x280040) 80 #define MSS_DPSHSR_REG_PCIE_CLK_SEL 0x8 81 82 /******************************************************************************* 83 * RTC Configuration 84 ******************************************************************************/ 85 #define MVEBU_RTC_BASE (0x284000) 86 #define MVEBU_RTC_STATUS_REG (MVEBU_RTC_BASE + 0x0) 87 #define MVEBU_RTC_STATUS_ALARM1_MASK 0x1 88 #define MVEBU_RTC_STATUS_ALARM2_MASK 0x2 89 #define MVEBU_RTC_IRQ_1_CONFIG_REG (MVEBU_RTC_BASE + 0x4) 90 #define MVEBU_RTC_IRQ_2_CONFIG_REG (MVEBU_RTC_BASE + 0x8) 91 #define MVEBU_RTC_TIME_REG (MVEBU_RTC_BASE + 0xC) 92 #define MVEBU_RTC_ALARM_1_REG (MVEBU_RTC_BASE + 0x10) 93 #define MVEBU_RTC_ALARM_2_REG (MVEBU_RTC_BASE + 0x14) 94 #define MVEBU_RTC_CCR_REG (MVEBU_RTC_BASE + 0x18) 95 #define MVEBU_RTC_NOMINAL_TIMING 0x2000 96 #define MVEBU_RTC_NOMINAL_TIMING_MASK 0x7FFF 97 #define MVEBU_RTC_TEST_CONFIG_REG (MVEBU_RTC_BASE + 0x1C) 98 #define MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG (MVEBU_RTC_BASE + 0x80) 99 #define MVEBU_RTC_WRCLK_PERIOD_MASK 0xFFFF 100 #define MVEBU_RTC_WRCLK_PERIOD_DEFAULT 0x3FF 101 #define MVEBU_RTC_WRCLK_SETUP_OFFS 16 102 #define MVEBU_RTC_WRCLK_SETUP_MASK 0xFFFF0000 103 #define MVEBU_RTC_WRCLK_SETUP_DEFAULT 0x29 104 #define MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG (MVEBU_RTC_BASE + 0x84) 105 #define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF 106 #define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F 107 108 enum axi_attr { 109 AXI_ADUNIT_ATTR = 0, 110 AXI_COMUNIT_ATTR, 111 AXI_EIP197_ATTR, 112 AXI_USB3D_ATTR, 113 AXI_USB3H0_ATTR, 114 AXI_USB3H1_ATTR, 115 AXI_SATA0_ATTR, 116 AXI_SATA1_ATTR, 117 AXI_DAP_ATTR, 118 AXI_DFX_ATTR, 119 AXI_DBG_TRC_ATTR = 12, 120 AXI_SDIO_ATTR, 121 AXI_MSS_ATTR, 122 AXI_MAX_ATTR, 123 }; 124 125 /* Most stream IDS are configured centrally in the CP-110 RFU 126 * but some are configured inside the unit registers 127 */ 128 #define RFU_STREAM_ID_BASE (0x450000) 129 #define USB3H_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0xC) 130 #define USB3H_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x10) 131 #define SATA_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x14) 132 #define SATA_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x18) 133 134 #define CP_DMA_0_STREAM_ID_REG (0x6B0010) 135 #define CP_DMA_1_STREAM_ID_REG (0x6D0010) 136 137 /* We allocate IDs 128-255 for PCIe */ 138 #define MAX_STREAM_ID (0x80) 139 140 uintptr_t stream_id_reg[] = { 141 USB3H_0_STREAM_ID_REG, 142 USB3H_1_STREAM_ID_REG, 143 CP_DMA_0_STREAM_ID_REG, 144 CP_DMA_1_STREAM_ID_REG, 145 SATA_0_STREAM_ID_REG, 146 SATA_1_STREAM_ID_REG, 147 0 148 }; 149 150 static void cp110_errata_wa_init(uintptr_t base) 151 { 152 uint32_t data; 153 154 /* ERRATA GL-4076863: 155 * Reset value for global_secure_enable inputs must be changed 156 * from '1' to '0'. 157 * When asserted, only "secured" transactions can enter IHB 158 * configuration space. 159 * However, blocking AXI transactions is performed by IOB. 160 * Performing it also at IHB/HB complicates programming model. 161 * 162 * Enable non-secure access in SOC configuration register 163 */ 164 data = mmio_read_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM)); 165 data &= ~MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK; 166 mmio_write_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM), data); 167 } 168 169 static void cp110_pcie_clk_cfg(uintptr_t base) 170 { 171 uint32_t pcie0_clk, pcie1_clk, reg; 172 173 /* 174 * Determine the pcie0/1 clock direction (input/output) from the 175 * sample at reset. 176 */ 177 reg = mmio_read_32(base + MVEBU_SAMPLE_AT_RESET_REG); 178 pcie0_clk = (reg & SAR_PCIE0_CLK_CFG_MASK) >> SAR_PCIE0_CLK_CFG_OFFSET; 179 pcie1_clk = (reg & SAR_PCIE1_CLK_CFG_MASK) >> SAR_PCIE1_CLK_CFG_OFFSET; 180 181 /* CP110 revision A2 */ 182 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2) { 183 /* 184 * PCIe Reference Clock Buffer Control register must be 185 * set according to the clock direction (input/output) 186 */ 187 reg = mmio_read_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL); 188 reg &= ~(PCIE0_REFCLK_BUFF_SOURCE | PCIE1_REFCLK_BUFF_SOURCE); 189 if (!pcie0_clk) 190 reg |= PCIE0_REFCLK_BUFF_SOURCE; 191 if (!pcie1_clk) 192 reg |= PCIE1_REFCLK_BUFF_SOURCE; 193 194 mmio_write_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL, reg); 195 } 196 197 /* CP110 revision A1 */ 198 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A1) { 199 if (!pcie0_clk || !pcie1_clk) { 200 /* 201 * if one of the pcie clocks is set to input, 202 * we need to set mss_push[131] field, otherwise, 203 * the pcie clock might not work. 204 */ 205 reg = mmio_read_32(base + MVEBU_CP_MSS_DPSHSR_REG); 206 reg |= MSS_DPSHSR_REG_PCIE_CLK_SEL; 207 mmio_write_32(base + MVEBU_CP_MSS_DPSHSR_REG, reg); 208 } 209 } 210 } 211 212 /* Set a unique stream id for all DMA capable devices */ 213 static void cp110_stream_id_init(uintptr_t base, uint32_t stream_id) 214 { 215 int i = 0; 216 217 while (stream_id_reg[i]) { 218 if (i > MAX_STREAM_ID_PER_CP) { 219 NOTICE("Only first %d (maximum) Stream IDs allocated\n", 220 MAX_STREAM_ID_PER_CP); 221 return; 222 } 223 224 if ((stream_id_reg[i] == CP_DMA_0_STREAM_ID_REG) || 225 (stream_id_reg[i] == CP_DMA_1_STREAM_ID_REG)) 226 mmio_write_32(base + stream_id_reg[i], 227 stream_id << 16 | stream_id); 228 else 229 mmio_write_32(base + stream_id_reg[i], stream_id); 230 231 /* SATA port 0/1 are in the same SATA unit, and they should use 232 * the same STREAM ID number 233 */ 234 if (stream_id_reg[i] != SATA_0_STREAM_ID_REG) 235 stream_id++; 236 237 i++; 238 } 239 } 240 241 static void cp110_axi_attr_init(uintptr_t base) 242 { 243 uint32_t index, data; 244 245 /* Initialize AXI attributes for Armada-7K/8K SoC */ 246 247 /* Go over the AXI attributes and set Ax-Cache and Ax-Domain */ 248 for (index = 0; index < AXI_MAX_ATTR; index++) { 249 switch (index) { 250 /* DFX and MSS unit works with no coherent only - 251 * there's no option to configure the Ax-Cache and Ax-Domain 252 */ 253 case AXI_DFX_ATTR: 254 case AXI_MSS_ATTR: 255 continue; 256 default: 257 /* Set Ax-Cache as cacheable, no allocate, modifiable, 258 * bufferable 259 * The values are different because Read & Write 260 * definition is different in Ax-Cache 261 */ 262 data = mmio_read_32(base + MVEBU_AXI_ATTR_REG(index)); 263 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; 264 data |= (CACHE_ATTR_WRITE_ALLOC | 265 CACHE_ATTR_CACHEABLE | 266 CACHE_ATTR_BUFFERABLE) << 267 MVEBU_AXI_ATTR_ARCACHE_OFFSET; 268 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; 269 data |= (CACHE_ATTR_READ_ALLOC | 270 CACHE_ATTR_CACHEABLE | 271 CACHE_ATTR_BUFFERABLE) << 272 MVEBU_AXI_ATTR_AWCACHE_OFFSET; 273 /* Set Ax-Domain as Outer domain */ 274 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; 275 data |= DOMAIN_OUTER_SHAREABLE << 276 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; 277 data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; 278 data |= DOMAIN_OUTER_SHAREABLE << 279 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; 280 mmio_write_32(base + MVEBU_AXI_ATTR_REG(index), data); 281 } 282 } 283 284 /* SATA IOCC supported, cache attributes 285 * for SATA MBUS to AXI configuration. 286 */ 287 data = mmio_read_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG); 288 data &= ~MVEBU_SATA_M2A_AXI_AWCACHE_MASK; 289 data |= (CACHE_ATTR_WRITE_ALLOC | 290 CACHE_ATTR_CACHEABLE | 291 CACHE_ATTR_BUFFERABLE) << 292 MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET; 293 data &= ~MVEBU_SATA_M2A_AXI_ARCACHE_MASK; 294 data |= (CACHE_ATTR_READ_ALLOC | 295 CACHE_ATTR_CACHEABLE | 296 CACHE_ATTR_BUFFERABLE) << 297 MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET; 298 mmio_write_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG, data); 299 300 /* Set all IO's AXI attribute to non-secure access. */ 301 for (index = 0; index < MVEBU_AXI_PROT_REGS_NUM; index++) 302 mmio_write_32(base + MVEBU_AXI_PROT_REG(index), 303 DOMAIN_SYSTEM_SHAREABLE); 304 } 305 306 void cp110_amb_init(uintptr_t base) 307 { 308 uint32_t reg; 309 310 /* Open AMB bridge Window to Access COMPHY/MDIO registers */ 311 reg = mmio_read_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0)); 312 reg &= ~(MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK | 313 MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK); 314 reg |= (0x7ff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) | 315 (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET); 316 mmio_write_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0), reg); 317 } 318 319 static void cp110_rtc_init(uintptr_t base) 320 { 321 /* Update MBus timing parameters before accessing RTC registers */ 322 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG, 323 MVEBU_RTC_WRCLK_PERIOD_MASK, 324 MVEBU_RTC_WRCLK_PERIOD_DEFAULT); 325 326 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG, 327 MVEBU_RTC_WRCLK_SETUP_MASK, 328 MVEBU_RTC_WRCLK_SETUP_DEFAULT << 329 MVEBU_RTC_WRCLK_SETUP_OFFS); 330 331 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG, 332 MVEBU_RTC_READ_OUTPUT_DELAY_MASK, 333 MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT); 334 335 /* 336 * Issue reset to the RTC if Clock Correction register 337 * contents did not sustain the reboot/power-on. 338 */ 339 if ((mmio_read_32(base + MVEBU_RTC_CCR_REG) & 340 MVEBU_RTC_NOMINAL_TIMING_MASK) != MVEBU_RTC_NOMINAL_TIMING) { 341 /* Reset Test register */ 342 mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0); 343 mdelay(500); 344 345 /* Reset Status register */ 346 mmio_write_32(base + MVEBU_RTC_STATUS_REG, 347 (MVEBU_RTC_STATUS_ALARM1_MASK | 348 MVEBU_RTC_STATUS_ALARM2_MASK)); 349 udelay(62); 350 351 /* Turn off Int1 and Int2 sources & clear the Alarm count */ 352 mmio_write_32(base + MVEBU_RTC_IRQ_1_CONFIG_REG, 0); 353 mmio_write_32(base + MVEBU_RTC_IRQ_2_CONFIG_REG, 0); 354 mmio_write_32(base + MVEBU_RTC_ALARM_1_REG, 0); 355 mmio_write_32(base + MVEBU_RTC_ALARM_2_REG, 0); 356 357 /* Setup nominal register access timing */ 358 mmio_write_32(base + MVEBU_RTC_CCR_REG, 359 MVEBU_RTC_NOMINAL_TIMING); 360 361 /* Reset Status register */ 362 mmio_write_32(base + MVEBU_RTC_STATUS_REG, 363 (MVEBU_RTC_STATUS_ALARM1_MASK | 364 MVEBU_RTC_STATUS_ALARM2_MASK)); 365 udelay(50); 366 } 367 } 368 369 static void cp110_amb_adec_init(uintptr_t base) 370 { 371 /* enable AXI-MBUS by clearing "Bridge Windows Disable" */ 372 mmio_clrbits_32(base + MVEBU_BRIDGE_WIN_DIS_REG, 373 (1 << MVEBU_BRIDGE_WIN_DIS_OFF)); 374 375 /* configure AXI-MBUS windows for CP */ 376 init_amb_adec(base); 377 } 378 379 void cp110_init(uintptr_t cp110_base, uint32_t stream_id) 380 { 381 INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base); 382 383 /* configure IOB windows for CP0*/ 384 init_iob(cp110_base); 385 386 /* configure AXI-MBUS windows for CP0*/ 387 cp110_amb_adec_init(cp110_base); 388 389 /* configure axi for CP0*/ 390 cp110_axi_attr_init(cp110_base); 391 392 /* Execute SW WA for erratas */ 393 cp110_errata_wa_init(cp110_base); 394 395 /* Confiure pcie clock according to clock direction */ 396 cp110_pcie_clk_cfg(cp110_base); 397 398 /* configure stream id for CP0 */ 399 cp110_stream_id_init(cp110_base, stream_id); 400 401 /* Open AMB bridge for comphy for CP0 & CP1*/ 402 cp110_amb_init(cp110_base); 403 404 /* Reset RTC if needed */ 405 cp110_rtc_init(cp110_base); 406 } 407 408 /* Do the minimal setup required to configure the CP in BLE */ 409 void cp110_ble_init(uintptr_t cp110_base) 410 { 411 #if PCI_EP_SUPPORT 412 INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base); 413 414 cp110_amb_init(cp110_base); 415 416 /* Configure PCIe clock */ 417 cp110_pcie_clk_cfg(cp110_base); 418 419 /* Configure PCIe endpoint */ 420 ble_plat_pcie_ep_setup(); 421 #endif 422 } 423