1 /* 2 * Copyright (C) 2018-2020 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* CP110 Marvell SoC driver */ 9 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <drivers/marvell/amb_adec.h> 13 #include <drivers/marvell/iob.h> 14 #include <drivers/marvell/mochi/cp110_setup.h> 15 #include <drivers/rambus/trng_ip_76.h> 16 17 #include <plat_marvell.h> 18 19 /* 20 * AXI Configuration. 21 */ 22 23 /* Used for Units of CP-110 (e.g. USB device, USB Host, and etc) */ 24 #define MVEBU_AXI_ATTR_OFFSET (0x441300) 25 #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_OFFSET + \ 26 0x4 * index) 27 28 /* AXI Protection bits */ 29 #define MVEBU_AXI_PROT_OFFSET (0x441200) 30 31 /* AXI Protection regs */ 32 #define MVEBU_AXI_PROT_REG(index) ((index <= 4) ? \ 33 (MVEBU_AXI_PROT_OFFSET + \ 34 0x4 * index) : \ 35 (MVEBU_AXI_PROT_OFFSET + 0x18)) 36 #define MVEBU_AXI_PROT_REGS_NUM (6) 37 38 #define MVEBU_SOC_CFGS_OFFSET (0x441900) 39 #define MVEBU_SOC_CFG_REG(index) (MVEBU_SOC_CFGS_OFFSET + \ 40 0x4 * index) 41 #define MVEBU_SOC_CFG_REG_NUM (0) 42 #define MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK (0xE) 43 44 /* SATA3 MBUS to AXI regs */ 45 #define MVEBU_BRIDGE_WIN_DIS_REG (MVEBU_SOC_CFGS_OFFSET + 0x10) 46 #define MVEBU_BRIDGE_WIN_DIS_OFF (0x0) 47 48 /* SATA3 MBUS to AXI regs */ 49 #define MVEBU_SATA_M2A_AXI_PORT_CTRL_REG (0x54ff04) 50 51 /* AXI to MBUS bridge registers */ 52 #define MVEBU_AMB_IP_OFFSET (0x13ff00) 53 #define MVEBU_AMB_IP_BRIDGE_WIN_REG(win) (MVEBU_AMB_IP_OFFSET + \ 54 (win * 0x8)) 55 #define MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET 0 56 #define MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK \ 57 (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET) 58 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET 16 59 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK \ 60 (0xffffu << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) 61 62 #define MVEBU_SAMPLE_AT_RESET_REG (0x440600) 63 #define SAR_PCIE1_CLK_CFG_OFFSET 31 64 #define SAR_PCIE1_CLK_CFG_MASK (0x1u << SAR_PCIE1_CLK_CFG_OFFSET) 65 #define SAR_PCIE0_CLK_CFG_OFFSET 30 66 #define SAR_PCIE0_CLK_CFG_MASK (0x1 << SAR_PCIE0_CLK_CFG_OFFSET) 67 #define SAR_I2C_INIT_EN_OFFSET 24 68 #define SAR_I2C_INIT_EN_MASK (1 << SAR_I2C_INIT_EN_OFFSET) 69 70 /******************************************************************************* 71 * PCIE clock buffer control 72 ******************************************************************************/ 73 #define MVEBU_PCIE_REF_CLK_BUF_CTRL (0x4404F0) 74 #define PCIE1_REFCLK_BUFF_SOURCE 0x800 75 #define PCIE0_REFCLK_BUFF_SOURCE 0x400 76 77 /******************************************************************************* 78 * MSS Device Push Set Register 79 ******************************************************************************/ 80 #define MVEBU_CP_MSS_DPSHSR_REG (0x280040) 81 #define MSS_DPSHSR_REG_PCIE_CLK_SEL 0x8 82 83 /******************************************************************************* 84 * RTC Configuration 85 ******************************************************************************/ 86 #define MVEBU_RTC_BASE (0x284000) 87 #define MVEBU_RTC_STATUS_REG (MVEBU_RTC_BASE + 0x0) 88 #define MVEBU_RTC_STATUS_ALARM1_MASK 0x1 89 #define MVEBU_RTC_STATUS_ALARM2_MASK 0x2 90 #define MVEBU_RTC_IRQ_1_CONFIG_REG (MVEBU_RTC_BASE + 0x4) 91 #define MVEBU_RTC_IRQ_2_CONFIG_REG (MVEBU_RTC_BASE + 0x8) 92 #define MVEBU_RTC_TIME_REG (MVEBU_RTC_BASE + 0xC) 93 #define MVEBU_RTC_ALARM_1_REG (MVEBU_RTC_BASE + 0x10) 94 #define MVEBU_RTC_ALARM_2_REG (MVEBU_RTC_BASE + 0x14) 95 #define MVEBU_RTC_CCR_REG (MVEBU_RTC_BASE + 0x18) 96 #define MVEBU_RTC_NOMINAL_TIMING 0x2000 97 #define MVEBU_RTC_NOMINAL_TIMING_MASK 0x7FFF 98 #define MVEBU_RTC_TEST_CONFIG_REG (MVEBU_RTC_BASE + 0x1C) 99 #define MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG (MVEBU_RTC_BASE + 0x80) 100 #define MVEBU_RTC_WRCLK_PERIOD_MASK 0xFFFF 101 #define MVEBU_RTC_WRCLK_PERIOD_DEFAULT 0x3FF 102 #define MVEBU_RTC_WRCLK_SETUP_OFFS 16 103 #define MVEBU_RTC_WRCLK_SETUP_MASK 0xFFFF0000 104 #define MVEBU_RTC_WRCLK_SETUP_DEFAULT 0x29 105 #define MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG (MVEBU_RTC_BASE + 0x84) 106 #define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF 107 #define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F 108 109 /******************************************************************************* 110 * TRNG Configuration 111 ******************************************************************************/ 112 #define MVEBU_TRNG_BASE (0x760000) 113 114 enum axi_attr { 115 AXI_ADUNIT_ATTR = 0, 116 AXI_COMUNIT_ATTR, 117 AXI_EIP197_ATTR, 118 AXI_USB3D_ATTR, 119 AXI_USB3H0_ATTR, 120 AXI_USB3H1_ATTR, 121 AXI_SATA0_ATTR, 122 AXI_SATA1_ATTR, 123 AXI_DAP_ATTR, 124 AXI_DFX_ATTR, 125 AXI_DBG_TRC_ATTR = 12, 126 AXI_SDIO_ATTR, 127 AXI_MSS_ATTR, 128 AXI_MAX_ATTR, 129 }; 130 131 /* Most stream IDS are configured centrally in the CP-110 RFU 132 * but some are configured inside the unit registers 133 */ 134 #define RFU_STREAM_ID_BASE (0x450000) 135 #define USB3H_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0xC) 136 #define USB3H_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x10) 137 #define SATA_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x14) 138 #define SATA_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x18) 139 #define SDIO_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x28) 140 141 #define CP_DMA_0_STREAM_ID_REG (0x6B0010) 142 #define CP_DMA_1_STREAM_ID_REG (0x6D0010) 143 144 /* We allocate IDs 128-255 for PCIe */ 145 #define MAX_STREAM_ID (0x80) 146 147 static uintptr_t stream_id_reg[] = { 148 USB3H_0_STREAM_ID_REG, 149 USB3H_1_STREAM_ID_REG, 150 CP_DMA_0_STREAM_ID_REG, 151 CP_DMA_1_STREAM_ID_REG, 152 SATA_0_STREAM_ID_REG, 153 SATA_1_STREAM_ID_REG, 154 SDIO_STREAM_ID_REG, 155 0 156 }; 157 158 static void cp110_errata_wa_init(uintptr_t base) 159 { 160 uint32_t data; 161 162 /* ERRATA GL-4076863: 163 * Reset value for global_secure_enable inputs must be changed 164 * from '1' to '0'. 165 * When asserted, only "secured" transactions can enter IHB 166 * configuration space. 167 * However, blocking AXI transactions is performed by IOB. 168 * Performing it also at IHB/HB complicates programming model. 169 * 170 * Enable non-secure access in SOC configuration register 171 */ 172 data = mmio_read_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM)); 173 data &= ~MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK; 174 mmio_write_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM), data); 175 } 176 177 static void cp110_pcie_clk_cfg(uintptr_t base) 178 { 179 uint32_t pcie0_clk, pcie1_clk, reg; 180 181 /* 182 * Determine the pcie0/1 clock direction (input/output) from the 183 * sample at reset. 184 */ 185 reg = mmio_read_32(base + MVEBU_SAMPLE_AT_RESET_REG); 186 pcie0_clk = (reg & SAR_PCIE0_CLK_CFG_MASK) >> SAR_PCIE0_CLK_CFG_OFFSET; 187 pcie1_clk = (reg & SAR_PCIE1_CLK_CFG_MASK) >> SAR_PCIE1_CLK_CFG_OFFSET; 188 189 /* CP110 revision A2 or CN913x */ 190 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2 || 191 cp110_device_id_get(base) == MVEBU_CN9130_DEV_ID) { 192 /* 193 * PCIe Reference Clock Buffer Control register must be 194 * set according to the clock direction (input/output) 195 */ 196 reg = mmio_read_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL); 197 reg &= ~(PCIE0_REFCLK_BUFF_SOURCE | PCIE1_REFCLK_BUFF_SOURCE); 198 if (!pcie0_clk) 199 reg |= PCIE0_REFCLK_BUFF_SOURCE; 200 if (!pcie1_clk) 201 reg |= PCIE1_REFCLK_BUFF_SOURCE; 202 203 mmio_write_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL, reg); 204 } 205 206 /* CP110 revision A1 */ 207 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A1) { 208 if (!pcie0_clk || !pcie1_clk) { 209 /* 210 * if one of the pcie clocks is set to input, 211 * we need to set mss_push[131] field, otherwise, 212 * the pcie clock might not work. 213 */ 214 reg = mmio_read_32(base + MVEBU_CP_MSS_DPSHSR_REG); 215 reg |= MSS_DPSHSR_REG_PCIE_CLK_SEL; 216 mmio_write_32(base + MVEBU_CP_MSS_DPSHSR_REG, reg); 217 } 218 } 219 } 220 221 /* Set a unique stream id for all DMA capable devices */ 222 static void cp110_stream_id_init(uintptr_t base, uint32_t stream_id) 223 { 224 int i = 0; 225 226 while (stream_id_reg[i]) { 227 if (i > MAX_STREAM_ID_PER_CP) { 228 NOTICE("Only first %d (maximum) Stream IDs allocated\n", 229 MAX_STREAM_ID_PER_CP); 230 return; 231 } 232 233 if ((stream_id_reg[i] == CP_DMA_0_STREAM_ID_REG) || 234 (stream_id_reg[i] == CP_DMA_1_STREAM_ID_REG)) 235 mmio_write_32(base + stream_id_reg[i], 236 stream_id << 16 | stream_id); 237 else 238 mmio_write_32(base + stream_id_reg[i], stream_id); 239 240 /* SATA port 0/1 are in the same SATA unit, and they should use 241 * the same STREAM ID number 242 */ 243 if (stream_id_reg[i] != SATA_0_STREAM_ID_REG) 244 stream_id++; 245 246 i++; 247 } 248 } 249 250 static void cp110_axi_attr_init(uintptr_t base) 251 { 252 uint32_t index, data; 253 254 /* Initialize AXI attributes for Armada-7K/8K SoC */ 255 256 /* Go over the AXI attributes and set Ax-Cache and Ax-Domain */ 257 for (index = 0; index < AXI_MAX_ATTR; index++) { 258 switch (index) { 259 /* DFX and MSS unit works with no coherent only - 260 * there's no option to configure the Ax-Cache and Ax-Domain 261 */ 262 case AXI_DFX_ATTR: 263 case AXI_MSS_ATTR: 264 continue; 265 default: 266 /* Set Ax-Cache as cacheable, no allocate, modifiable, 267 * bufferable 268 * The values are different because Read & Write 269 * definition is different in Ax-Cache 270 */ 271 data = mmio_read_32(base + MVEBU_AXI_ATTR_REG(index)); 272 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; 273 data |= (CACHE_ATTR_WRITE_ALLOC | 274 CACHE_ATTR_CACHEABLE | 275 CACHE_ATTR_BUFFERABLE) << 276 MVEBU_AXI_ATTR_ARCACHE_OFFSET; 277 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; 278 data |= (CACHE_ATTR_READ_ALLOC | 279 CACHE_ATTR_CACHEABLE | 280 CACHE_ATTR_BUFFERABLE) << 281 MVEBU_AXI_ATTR_AWCACHE_OFFSET; 282 /* Set Ax-Domain as Outer domain */ 283 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; 284 data |= DOMAIN_OUTER_SHAREABLE << 285 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; 286 data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; 287 data |= DOMAIN_OUTER_SHAREABLE << 288 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; 289 mmio_write_32(base + MVEBU_AXI_ATTR_REG(index), data); 290 } 291 } 292 293 /* SATA IOCC supported, cache attributes 294 * for SATA MBUS to AXI configuration. 295 */ 296 data = mmio_read_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG); 297 data &= ~MVEBU_SATA_M2A_AXI_AWCACHE_MASK; 298 data |= (CACHE_ATTR_WRITE_ALLOC | 299 CACHE_ATTR_CACHEABLE | 300 CACHE_ATTR_BUFFERABLE) << 301 MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET; 302 data &= ~MVEBU_SATA_M2A_AXI_ARCACHE_MASK; 303 data |= (CACHE_ATTR_READ_ALLOC | 304 CACHE_ATTR_CACHEABLE | 305 CACHE_ATTR_BUFFERABLE) << 306 MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET; 307 mmio_write_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG, data); 308 309 /* Set all IO's AXI attribute to non-secure access. */ 310 for (index = 0; index < MVEBU_AXI_PROT_REGS_NUM; index++) 311 mmio_write_32(base + MVEBU_AXI_PROT_REG(index), 312 DOMAIN_SYSTEM_SHAREABLE); 313 } 314 315 void cp110_amb_init(uintptr_t base) 316 { 317 uint32_t reg; 318 319 /* Open AMB bridge Window to Access COMPHY/MDIO registers */ 320 reg = mmio_read_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0)); 321 reg &= ~(MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK | 322 MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK); 323 reg |= (0x7ff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) | 324 (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET); 325 mmio_write_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0), reg); 326 } 327 328 static void cp110_rtc_init(uintptr_t base) 329 { 330 /* Update MBus timing parameters before accessing RTC registers */ 331 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG, 332 MVEBU_RTC_WRCLK_PERIOD_MASK, 333 MVEBU_RTC_WRCLK_PERIOD_DEFAULT); 334 335 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG, 336 MVEBU_RTC_WRCLK_SETUP_MASK, 337 MVEBU_RTC_WRCLK_SETUP_DEFAULT << 338 MVEBU_RTC_WRCLK_SETUP_OFFS); 339 340 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG, 341 MVEBU_RTC_READ_OUTPUT_DELAY_MASK, 342 MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT); 343 344 /* 345 * Issue reset to the RTC if Clock Correction register 346 * contents did not sustain the reboot/power-on. 347 */ 348 if ((mmio_read_32(base + MVEBU_RTC_CCR_REG) & 349 MVEBU_RTC_NOMINAL_TIMING_MASK) != MVEBU_RTC_NOMINAL_TIMING) { 350 /* Reset Test register */ 351 mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0); 352 mdelay(500); 353 354 /* Reset Status register */ 355 mmio_write_32(base + MVEBU_RTC_STATUS_REG, 356 (MVEBU_RTC_STATUS_ALARM1_MASK | 357 MVEBU_RTC_STATUS_ALARM2_MASK)); 358 udelay(62); 359 360 /* Turn off Int1 and Int2 sources & clear the Alarm count */ 361 mmio_write_32(base + MVEBU_RTC_IRQ_1_CONFIG_REG, 0); 362 mmio_write_32(base + MVEBU_RTC_IRQ_2_CONFIG_REG, 0); 363 mmio_write_32(base + MVEBU_RTC_ALARM_1_REG, 0); 364 mmio_write_32(base + MVEBU_RTC_ALARM_2_REG, 0); 365 366 /* Setup nominal register access timing */ 367 mmio_write_32(base + MVEBU_RTC_CCR_REG, 368 MVEBU_RTC_NOMINAL_TIMING); 369 370 /* Reset Status register */ 371 mmio_write_32(base + MVEBU_RTC_STATUS_REG, 372 (MVEBU_RTC_STATUS_ALARM1_MASK | 373 MVEBU_RTC_STATUS_ALARM2_MASK)); 374 udelay(50); 375 } 376 } 377 378 static void cp110_amb_adec_init(uintptr_t base) 379 { 380 /* enable AXI-MBUS by clearing "Bridge Windows Disable" */ 381 mmio_clrbits_32(base + MVEBU_BRIDGE_WIN_DIS_REG, 382 (1 << MVEBU_BRIDGE_WIN_DIS_OFF)); 383 384 /* configure AXI-MBUS windows for CP */ 385 init_amb_adec(base); 386 } 387 388 static void cp110_trng_init(uintptr_t base) 389 { 390 static bool done; 391 int ret; 392 393 if (!done) { 394 ret = eip76_rng_probe(base + MVEBU_TRNG_BASE); 395 if (ret != 0) { 396 ERROR("Failed to init TRNG @ 0x%lx\n", base); 397 return; 398 } 399 done = true; 400 } 401 } 402 void cp110_init(uintptr_t cp110_base, uint32_t stream_id) 403 { 404 INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base); 405 406 /* configure IOB windows for CP0*/ 407 init_iob(cp110_base); 408 409 /* configure AXI-MBUS windows for CP0*/ 410 cp110_amb_adec_init(cp110_base); 411 412 /* configure axi for CP0*/ 413 cp110_axi_attr_init(cp110_base); 414 415 /* Execute SW WA for erratas */ 416 cp110_errata_wa_init(cp110_base); 417 418 /* Confiure pcie clock according to clock direction */ 419 cp110_pcie_clk_cfg(cp110_base); 420 421 /* configure stream id for CP0 */ 422 cp110_stream_id_init(cp110_base, stream_id); 423 424 /* Open AMB bridge for comphy for CP0 & CP1*/ 425 cp110_amb_init(cp110_base); 426 427 /* Reset RTC if needed */ 428 cp110_rtc_init(cp110_base); 429 430 /* TRNG init - for CP0 only */ 431 cp110_trng_init(cp110_base); 432 } 433 434 /* Do the minimal setup required to configure the CP in BLE */ 435 void cp110_ble_init(uintptr_t cp110_base) 436 { 437 #if PCI_EP_SUPPORT 438 INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base); 439 440 cp110_amb_init(cp110_base); 441 442 /* Configure PCIe clock */ 443 cp110_pcie_clk_cfg(cp110_base); 444 445 /* Configure PCIe endpoint */ 446 ble_plat_pcie_ep_setup(); 447 #endif 448 } 449