1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* CP110 Marvell SoC driver */ 9 10 #include <amb_adec.h> 11 #include <cp110_setup.h> 12 #include <debug.h> 13 #include <delay_timer.h> 14 #include <iob.h> 15 #include <plat_marvell.h> 16 17 /* 18 * AXI Configuration. 19 */ 20 21 /* Used for Units of CP-110 (e.g. USB device, USB Host, and etc) */ 22 #define MVEBU_AXI_ATTR_OFFSET (0x441300) 23 #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_OFFSET + \ 24 0x4 * index) 25 26 /* AXI Protection bits */ 27 #define MVEBU_AXI_PROT_OFFSET (0x441200) 28 29 /* AXI Protection regs */ 30 #define MVEBU_AXI_PROT_REG(index) ((index <= 4) ? \ 31 (MVEBU_AXI_PROT_OFFSET + \ 32 0x4 * index) : \ 33 (MVEBU_AXI_PROT_OFFSET + 0x18)) 34 #define MVEBU_AXI_PROT_REGS_NUM (6) 35 36 #define MVEBU_SOC_CFGS_OFFSET (0x441900) 37 #define MVEBU_SOC_CFG_REG(index) (MVEBU_SOC_CFGS_OFFSET + \ 38 0x4 * index) 39 #define MVEBU_SOC_CFG_REG_NUM (0) 40 #define MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK (0xE) 41 42 /* SATA3 MBUS to AXI regs */ 43 #define MVEBU_BRIDGE_WIN_DIS_REG (MVEBU_SOC_CFGS_OFFSET + 0x10) 44 #define MVEBU_BRIDGE_WIN_DIS_OFF (0x0) 45 46 /* SATA3 MBUS to AXI regs */ 47 #define MVEBU_SATA_M2A_AXI_PORT_CTRL_REG (0x54ff04) 48 49 /* AXI to MBUS bridge registers */ 50 #define MVEBU_AMB_IP_OFFSET (0x13ff00) 51 #define MVEBU_AMB_IP_BRIDGE_WIN_REG(win) (MVEBU_AMB_IP_OFFSET + \ 52 (win * 0x8)) 53 #define MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET 0 54 #define MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK \ 55 (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET) 56 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET 16 57 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK \ 58 (0xffff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) 59 60 #define MVEBU_SAMPLE_AT_RESET_REG (0x440600) 61 #define SAR_PCIE1_CLK_CFG_OFFSET 31 62 #define SAR_PCIE1_CLK_CFG_MASK (0x1 << SAR_PCIE1_CLK_CFG_OFFSET) 63 #define SAR_PCIE0_CLK_CFG_OFFSET 30 64 #define SAR_PCIE0_CLK_CFG_MASK (0x1 << SAR_PCIE0_CLK_CFG_OFFSET) 65 #define SAR_I2C_INIT_EN_OFFSET 24 66 #define SAR_I2C_INIT_EN_MASK (1 << SAR_I2C_INIT_EN_OFFSET) 67 68 /******************************************************************************* 69 * PCIE clock buffer control 70 ******************************************************************************/ 71 #define MVEBU_PCIE_REF_CLK_BUF_CTRL (0x4404F0) 72 #define PCIE1_REFCLK_BUFF_SOURCE 0x800 73 #define PCIE0_REFCLK_BUFF_SOURCE 0x400 74 75 /******************************************************************************* 76 * MSS Device Push Set Register 77 ******************************************************************************/ 78 #define MVEBU_CP_MSS_DPSHSR_REG (0x280040) 79 #define MSS_DPSHSR_REG_PCIE_CLK_SEL 0x8 80 81 /******************************************************************************* 82 * RTC Configuration 83 ******************************************************************************/ 84 #define MVEBU_RTC_BASE (0x284000) 85 #define MVEBU_RTC_STATUS_REG (MVEBU_RTC_BASE + 0x0) 86 #define MVEBU_RTC_STATUS_ALARM1_MASK 0x1 87 #define MVEBU_RTC_STATUS_ALARM2_MASK 0x2 88 #define MVEBU_RTC_IRQ_1_CONFIG_REG (MVEBU_RTC_BASE + 0x4) 89 #define MVEBU_RTC_IRQ_2_CONFIG_REG (MVEBU_RTC_BASE + 0x8) 90 #define MVEBU_RTC_TIME_REG (MVEBU_RTC_BASE + 0xC) 91 #define MVEBU_RTC_ALARM_1_REG (MVEBU_RTC_BASE + 0x10) 92 #define MVEBU_RTC_ALARM_2_REG (MVEBU_RTC_BASE + 0x14) 93 #define MVEBU_RTC_CCR_REG (MVEBU_RTC_BASE + 0x18) 94 #define MVEBU_RTC_NOMINAL_TIMING 0x2000 95 #define MVEBU_RTC_NOMINAL_TIMING_MASK 0x7FFF 96 #define MVEBU_RTC_TEST_CONFIG_REG (MVEBU_RTC_BASE + 0x1C) 97 #define MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG (MVEBU_RTC_BASE + 0x80) 98 #define MVEBU_RTC_WRCLK_PERIOD_MASK 0xFFFF 99 #define MVEBU_RTC_WRCLK_PERIOD_DEFAULT 0x3FF 100 #define MVEBU_RTC_WRCLK_SETUP_OFFS 16 101 #define MVEBU_RTC_WRCLK_SETUP_MASK 0xFFFF0000 102 #define MVEBU_RTC_WRCLK_SETUP_DEFAULT 0x29 103 #define MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG (MVEBU_RTC_BASE + 0x84) 104 #define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF 105 #define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F 106 107 enum axi_attr { 108 AXI_ADUNIT_ATTR = 0, 109 AXI_COMUNIT_ATTR, 110 AXI_EIP197_ATTR, 111 AXI_USB3D_ATTR, 112 AXI_USB3H0_ATTR, 113 AXI_USB3H1_ATTR, 114 AXI_SATA0_ATTR, 115 AXI_SATA1_ATTR, 116 AXI_DAP_ATTR, 117 AXI_DFX_ATTR, 118 AXI_DBG_TRC_ATTR = 12, 119 AXI_SDIO_ATTR, 120 AXI_MSS_ATTR, 121 AXI_MAX_ATTR, 122 }; 123 124 /* Most stream IDS are configured centrally in the CP-110 RFU 125 * but some are configured inside the unit registers 126 */ 127 #define RFU_STREAM_ID_BASE (0x450000) 128 #define USB3H_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0xC) 129 #define USB3H_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x10) 130 #define SATA_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x14) 131 #define SATA_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x18) 132 133 #define CP_DMA_0_STREAM_ID_REG (0x6B0010) 134 #define CP_DMA_1_STREAM_ID_REG (0x6D0010) 135 136 /* We allocate IDs 128-255 for PCIe */ 137 #define MAX_STREAM_ID (0x80) 138 139 uintptr_t stream_id_reg[] = { 140 USB3H_0_STREAM_ID_REG, 141 USB3H_1_STREAM_ID_REG, 142 CP_DMA_0_STREAM_ID_REG, 143 CP_DMA_1_STREAM_ID_REG, 144 SATA_0_STREAM_ID_REG, 145 SATA_1_STREAM_ID_REG, 146 0 147 }; 148 149 static void cp110_errata_wa_init(uintptr_t base) 150 { 151 uint32_t data; 152 153 /* ERRATA GL-4076863: 154 * Reset value for global_secure_enable inputs must be changed 155 * from '1' to '0'. 156 * When asserted, only "secured" transactions can enter IHB 157 * configuration space. 158 * However, blocking AXI transactions is performed by IOB. 159 * Performing it also at IHB/HB complicates programming model. 160 * 161 * Enable non-secure access in SOC configuration register 162 */ 163 data = mmio_read_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM)); 164 data &= ~MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK; 165 mmio_write_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM), data); 166 } 167 168 static void cp110_pcie_clk_cfg(uintptr_t base) 169 { 170 uint32_t pcie0_clk, pcie1_clk, reg; 171 172 /* 173 * Determine the pcie0/1 clock direction (input/output) from the 174 * sample at reset. 175 */ 176 reg = mmio_read_32(base + MVEBU_SAMPLE_AT_RESET_REG); 177 pcie0_clk = (reg & SAR_PCIE0_CLK_CFG_MASK) >> SAR_PCIE0_CLK_CFG_OFFSET; 178 pcie1_clk = (reg & SAR_PCIE1_CLK_CFG_MASK) >> SAR_PCIE1_CLK_CFG_OFFSET; 179 180 /* CP110 revision A2 */ 181 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2) { 182 /* 183 * PCIe Reference Clock Buffer Control register must be 184 * set according to the clock direction (input/output) 185 */ 186 reg = mmio_read_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL); 187 reg &= ~(PCIE0_REFCLK_BUFF_SOURCE | PCIE1_REFCLK_BUFF_SOURCE); 188 if (!pcie0_clk) 189 reg |= PCIE0_REFCLK_BUFF_SOURCE; 190 if (!pcie1_clk) 191 reg |= PCIE1_REFCLK_BUFF_SOURCE; 192 193 mmio_write_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL, reg); 194 } 195 196 /* CP110 revision A1 */ 197 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A1) { 198 if (!pcie0_clk || !pcie1_clk) { 199 /* 200 * if one of the pcie clocks is set to input, 201 * we need to set mss_push[131] field, otherwise, 202 * the pcie clock might not work. 203 */ 204 reg = mmio_read_32(base + MVEBU_CP_MSS_DPSHSR_REG); 205 reg |= MSS_DPSHSR_REG_PCIE_CLK_SEL; 206 mmio_write_32(base + MVEBU_CP_MSS_DPSHSR_REG, reg); 207 } 208 } 209 } 210 211 /* Set a unique stream id for all DMA capable devices */ 212 static void cp110_stream_id_init(uintptr_t base, uint32_t stream_id) 213 { 214 int i = 0; 215 216 while (stream_id_reg[i]) { 217 if (i > MAX_STREAM_ID_PER_CP) { 218 NOTICE("Only first %d (maximum) Stream IDs allocated\n", 219 MAX_STREAM_ID_PER_CP); 220 return; 221 } 222 223 if ((stream_id_reg[i] == CP_DMA_0_STREAM_ID_REG) || 224 (stream_id_reg[i] == CP_DMA_1_STREAM_ID_REG)) 225 mmio_write_32(base + stream_id_reg[i], 226 stream_id << 16 | stream_id); 227 else 228 mmio_write_32(base + stream_id_reg[i], stream_id); 229 230 /* SATA port 0/1 are in the same SATA unit, and they should use 231 * the same STREAM ID number 232 */ 233 if (stream_id_reg[i] != SATA_0_STREAM_ID_REG) 234 stream_id++; 235 236 i++; 237 } 238 } 239 240 static void cp110_axi_attr_init(uintptr_t base) 241 { 242 uint32_t index, data; 243 244 /* Initialize AXI attributes for Armada-7K/8K SoC */ 245 246 /* Go over the AXI attributes and set Ax-Cache and Ax-Domain */ 247 for (index = 0; index < AXI_MAX_ATTR; index++) { 248 switch (index) { 249 /* DFX and MSS unit works with no coherent only - 250 * there's no option to configure the Ax-Cache and Ax-Domain 251 */ 252 case AXI_DFX_ATTR: 253 case AXI_MSS_ATTR: 254 continue; 255 default: 256 /* Set Ax-Cache as cacheable, no allocate, modifiable, 257 * bufferable 258 * The values are different because Read & Write 259 * definition is different in Ax-Cache 260 */ 261 data = mmio_read_32(base + MVEBU_AXI_ATTR_REG(index)); 262 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; 263 data |= (CACHE_ATTR_WRITE_ALLOC | 264 CACHE_ATTR_CACHEABLE | 265 CACHE_ATTR_BUFFERABLE) << 266 MVEBU_AXI_ATTR_ARCACHE_OFFSET; 267 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; 268 data |= (CACHE_ATTR_READ_ALLOC | 269 CACHE_ATTR_CACHEABLE | 270 CACHE_ATTR_BUFFERABLE) << 271 MVEBU_AXI_ATTR_AWCACHE_OFFSET; 272 /* Set Ax-Domain as Outer domain */ 273 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; 274 data |= DOMAIN_OUTER_SHAREABLE << 275 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; 276 data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; 277 data |= DOMAIN_OUTER_SHAREABLE << 278 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; 279 mmio_write_32(base + MVEBU_AXI_ATTR_REG(index), data); 280 } 281 } 282 283 /* SATA IOCC supported, cache attributes 284 * for SATA MBUS to AXI configuration. 285 */ 286 data = mmio_read_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG); 287 data &= ~MVEBU_SATA_M2A_AXI_AWCACHE_MASK; 288 data |= (CACHE_ATTR_WRITE_ALLOC | 289 CACHE_ATTR_CACHEABLE | 290 CACHE_ATTR_BUFFERABLE) << 291 MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET; 292 data &= ~MVEBU_SATA_M2A_AXI_ARCACHE_MASK; 293 data |= (CACHE_ATTR_READ_ALLOC | 294 CACHE_ATTR_CACHEABLE | 295 CACHE_ATTR_BUFFERABLE) << 296 MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET; 297 mmio_write_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG, data); 298 299 /* Set all IO's AXI attribute to non-secure access. */ 300 for (index = 0; index < MVEBU_AXI_PROT_REGS_NUM; index++) 301 mmio_write_32(base + MVEBU_AXI_PROT_REG(index), 302 DOMAIN_SYSTEM_SHAREABLE); 303 } 304 305 static void amb_bridge_init(uintptr_t base) 306 { 307 uint32_t reg; 308 309 /* Open AMB bridge Window to Access COMPHY/MDIO registers */ 310 reg = mmio_read_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0)); 311 reg &= ~(MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK | 312 MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK); 313 reg |= (0x7ff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) | 314 (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET); 315 mmio_write_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0), reg); 316 } 317 318 static void cp110_rtc_init(uintptr_t base) 319 { 320 /* Update MBus timing parameters before accessing RTC registers */ 321 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG, 322 MVEBU_RTC_WRCLK_PERIOD_MASK, 323 MVEBU_RTC_WRCLK_PERIOD_DEFAULT); 324 325 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG, 326 MVEBU_RTC_WRCLK_SETUP_MASK, 327 MVEBU_RTC_WRCLK_SETUP_DEFAULT << 328 MVEBU_RTC_WRCLK_SETUP_OFFS); 329 330 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG, 331 MVEBU_RTC_READ_OUTPUT_DELAY_MASK, 332 MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT); 333 334 /* 335 * Issue reset to the RTC if Clock Correction register 336 * contents did not sustain the reboot/power-on. 337 */ 338 if ((mmio_read_32(base + MVEBU_RTC_CCR_REG) & 339 MVEBU_RTC_NOMINAL_TIMING_MASK) != MVEBU_RTC_NOMINAL_TIMING) { 340 /* Reset Test register */ 341 mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0); 342 mdelay(500); 343 344 /* Reset Status register */ 345 mmio_write_32(base + MVEBU_RTC_STATUS_REG, 346 (MVEBU_RTC_STATUS_ALARM1_MASK | 347 MVEBU_RTC_STATUS_ALARM2_MASK)); 348 udelay(62); 349 350 /* Turn off Int1 and Int2 sources & clear the Alarm count */ 351 mmio_write_32(base + MVEBU_RTC_IRQ_1_CONFIG_REG, 0); 352 mmio_write_32(base + MVEBU_RTC_IRQ_2_CONFIG_REG, 0); 353 mmio_write_32(base + MVEBU_RTC_ALARM_1_REG, 0); 354 mmio_write_32(base + MVEBU_RTC_ALARM_2_REG, 0); 355 356 /* Setup nominal register access timing */ 357 mmio_write_32(base + MVEBU_RTC_CCR_REG, 358 MVEBU_RTC_NOMINAL_TIMING); 359 360 /* Reset Status register */ 361 mmio_write_32(base + MVEBU_RTC_STATUS_REG, 362 (MVEBU_RTC_STATUS_ALARM1_MASK | 363 MVEBU_RTC_STATUS_ALARM2_MASK)); 364 udelay(50); 365 } 366 } 367 368 static void cp110_amb_adec_init(uintptr_t base) 369 { 370 /* enable AXI-MBUS by clearing "Bridge Windows Disable" */ 371 mmio_clrbits_32(base + MVEBU_BRIDGE_WIN_DIS_REG, 372 (1 << MVEBU_BRIDGE_WIN_DIS_OFF)); 373 374 /* configure AXI-MBUS windows for CP */ 375 init_amb_adec(base); 376 } 377 378 void cp110_init(uintptr_t cp110_base, uint32_t stream_id) 379 { 380 INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base); 381 382 /* configure IOB windows for CP0*/ 383 init_iob(cp110_base); 384 385 /* configure AXI-MBUS windows for CP0*/ 386 cp110_amb_adec_init(cp110_base); 387 388 /* configure axi for CP0*/ 389 cp110_axi_attr_init(cp110_base); 390 391 /* Execute SW WA for erratas */ 392 cp110_errata_wa_init(cp110_base); 393 394 /* Confiure pcie clock according to clock direction */ 395 cp110_pcie_clk_cfg(cp110_base); 396 397 /* configure stream id for CP0 */ 398 cp110_stream_id_init(cp110_base, stream_id); 399 400 /* Open AMB bridge for comphy for CP0 & CP1*/ 401 amb_bridge_init(cp110_base); 402 403 /* Reset RTC if needed */ 404 cp110_rtc_init(cp110_base); 405 } 406 407 /* Do the minimal setup required to configure the CP in BLE */ 408 void cp110_ble_init(uintptr_t cp110_base) 409 { 410 #if PCI_EP_SUPPORT 411 INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base); 412 413 amb_bridge_init(cp110_base); 414 415 /* Configure PCIe clock */ 416 cp110_pcie_clk_cfg(cp110_base); 417 418 /* Configure PCIe endpoint */ 419 ble_plat_pcie_ep_setup(); 420 #endif 421 } 422