1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2024, STMicroelectronics 4 */ 5 6 #ifndef __STM32_SYSCONF_H__ 7 #define __STM32_SYSCONF_H__ 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 #include <util.h> 12 13 /* syscon banks */ 14 enum syscon_banks { 15 SYSCON_SYSCFG, 16 SYSCON_A35SSC, 17 SYSCON_NB_BANKS 18 }; 19 20 #define SYSCON_ID(bank, offset) (((bank) << 16) | \ 21 ((offset) & GENMASK_32(15, 0))) 22 23 /* 24 * SYSCFG register offsets (base relative) 25 */ 26 #define SYSCFG_VDERAMCR SYSCON_ID(SYSCON_SYSCFG, 0x1800) 27 28 /* 29 * SYSCFG_VDERAMCR register offsets 30 */ 31 #define VDERAMCR_VDERAM_EN BIT(0) 32 #define VDERAMCR_MASK BIT(0) 33 34 /* 35 * A35SSC register offsets (base relative) 36 */ 37 #define A35SS_SSC_CHGCLKREQ SYSCON_ID(SYSCON_A35SSC, 0x0) 38 #define A35SS_SSC_PLL_FREQ1 SYSCON_ID(SYSCON_A35SSC, 0x80) 39 #define A35SS_SSC_PLL_FREQ2 SYSCON_ID(SYSCON_A35SSC, 0x90) 40 #define A35SS_SSC_PLL_EN SYSCON_ID(SYSCON_A35SSC, 0xA0) 41 42 #define A35SSC_M33CFG_ACCESS_CR SYSCON_ID(SYSCON_A35SSC, 0x2088) 43 #define A35SSC_M33_TZEN_CR SYSCON_ID(SYSCON_A35SSC, 0x20A0) 44 #define A35SSC_M33_INITSVTOR_CR SYSCON_ID(SYSCON_A35SSC, 0x20A4) 45 #define A35SSC_M33_INITNSVTOR_CR SYSCON_ID(SYSCON_A35SSC, 0x20A8) 46 47 /* 48 * A35SSC M33CFG_ACCESS_CR register 49 */ 50 #define A35SSC_M33_TZEN_CR_M33CFG_SEC BIT(0) 51 #define A35SSC_M33_TZEN_CR_M33CFG_PRIV BIT(1) 52 53 /* 54 * A35SSC M33_TZEN_CR register 55 */ 56 #define A35SSC_M33_TZEN_CR_CFG_SECEXT BIT(0) 57 58 /* 59 * A35SSC A35SS_SSC_CHGCLKREQ register 60 */ 61 #define A35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_EN BIT(0) 62 #define A35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_MASK BIT(0) 63 64 #define A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK BIT(1) 65 #define A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_SHIFT U(1) 66 67 /* 68 * A35SSC A35SS_SSC_PLL_FREQ1 register 69 */ 70 #define A35SS_SSC_PLL_FREQ1_FBDIV_MASK GENMASK_32(11, 0) 71 #define A35SS_SSC_PLL_FREQ1_FBDIV_SHIFT U(0) 72 73 #define A35SS_SSC_PLL_FREQ1_REFDIV_MASK GENMASK_32(21, 16) 74 #define A35SS_SSC_PLL_FREQ1_REFDIV_SHIFT U(16) 75 76 #define A35SS_SSC_PLL_FREQ1_MASK (A35SS_SSC_PLL_FREQ1_REFDIV_MASK | \ 77 A35SS_SSC_PLL_FREQ1_FBDIV_MASK) 78 79 /* 80 * A35SSC A35SS_SSC_PLL_FREQ2 register 81 */ 82 #define A35SS_SSC_PLL_FREQ2_POSTDIV1_MASK GENMASK_32(2, 0) 83 #define A35SS_SSC_PLL_FREQ2_POSTDIV1_SHIFT U(0) 84 85 #define A35SS_SSC_PLL_FREQ2_POSTDIV2_MASK GENMASK_32(5, 3) 86 #define A35SS_SSC_PLL_FREQ2_POSTDIV2_SHIFT U(3) 87 88 #define A35SS_SSC_PLL_FREQ2_MASK GENMASK_32(5, 0) 89 90 /* 91 * A35SSC A35SS_SSC_PLL_EN register 92 */ 93 #define A35SS_SSC_PLL_ENABLE_PD_EN BIT(0) 94 #define A35SS_SSC_PLL_ENABLE_PD_MASK BIT(0) 95 96 #define A35SS_SSC_PLL_ENABLE_LOCKP_MASK BIT(1) 97 98 #define A35SS_SSC_PLL_ENABLE_NRESET_SWPLL_FF_EN BIT(2) 99 #define A35SS_SSC_PLL_ENABLE_NRESET_SWPLL_FF_MASK BIT(2) 100 101 /* 102 * Write masked value is SYSCONF register 103 * @id: SYSCONF register ID, processed with SYSCON_ID() macro 104 * @value: Value to be written 105 * @bitmsk: Bit mask applied to @value 106 */ 107 void stm32mp_syscfg_write(uint32_t id, uint32_t value, uint32_t bitmsk); 108 109 /* 110 * Read SYSCONF reagister 111 * @id: SYSCONF register ID, processed with SYSCON_ID() macro 112 */ 113 uint32_t stm32mp_syscfg_read(uint32_t id); 114 115 /* 116 * Set safe reset state 117 * @status: True to enable safe reset, false to disable safe reset 118 */ 119 void stm32mp25_syscfg_set_safe_reset(bool status); 120 121 #endif /*__STM32_SYSCONF_H__*/ 122