1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2024, STMicroelectronics 4 */ 5 6 #ifndef __STM32_SYSCONF_H__ 7 #define __STM32_SYSCONF_H__ 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 #include <util.h> 12 13 /* syscon banks */ 14 enum syscon_banks { 15 SYSCON_SYSCFG, 16 SYSCON_A35SSC, 17 SYSCON_NB_BANKS 18 }; 19 20 #define SYSCON_ID(bank, offset) (((bank) << 16) | \ 21 ((offset) & GENMASK_32(15, 0))) 22 23 /* 24 * A35SSC register offsets (base relative) 25 */ 26 #define A35SS_SSC_CHGCLKREQ SYSCON_ID(SYSCON_A35SSC, 0x0) 27 #define A35SS_SSC_PLL_FREQ1 SYSCON_ID(SYSCON_A35SSC, 0x80) 28 #define A35SS_SSC_PLL_FREQ2 SYSCON_ID(SYSCON_A35SSC, 0x90) 29 #define A35SS_SSC_PLL_EN SYSCON_ID(SYSCON_A35SSC, 0xA0) 30 31 #define A35SSC_M33CFG_ACCESS_CR SYSCON_ID(SYSCON_A35SSC, 0x2088) 32 #define A35SSC_M33_TZEN_CR SYSCON_ID(SYSCON_A35SSC, 0x20A0) 33 #define A35SSC_M33_INITSVTOR_CR SYSCON_ID(SYSCON_A35SSC, 0x20A4) 34 #define A35SSC_M33_INITNSVTOR_CR SYSCON_ID(SYSCON_A35SSC, 0x20A8) 35 36 /* 37 * A35SSC M33CFG_ACCESS_CR register 38 */ 39 #define A35SSC_M33_TZEN_CR_M33CFG_SEC BIT(0) 40 #define A35SSC_M33_TZEN_CR_M33CFG_PRIV BIT(1) 41 42 /* 43 * A35SSC M33_TZEN_CR register 44 */ 45 #define A35SSC_M33_TZEN_CR_CFG_SECEXT BIT(0) 46 47 /* 48 * A35SSC A35SS_SSC_CHGCLKREQ register 49 */ 50 #define A35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_EN BIT(0) 51 #define A35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_MASK BIT(0) 52 53 #define A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK BIT(1) 54 #define A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_SHIFT U(1) 55 56 /* 57 * A35SSC A35SS_SSC_PLL_FREQ1 register 58 */ 59 #define A35SS_SSC_PLL_FREQ1_FBDIV_MASK GENMASK_32(11, 0) 60 #define A35SS_SSC_PLL_FREQ1_FBDIV_SHIFT U(0) 61 62 #define A35SS_SSC_PLL_FREQ1_REFDIV_MASK GENMASK_32(21, 16) 63 #define A35SS_SSC_PLL_FREQ1_REFDIV_SHIFT U(16) 64 65 #define A35SS_SSC_PLL_FREQ1_MASK (A35SS_SSC_PLL_FREQ1_REFDIV_MASK | \ 66 A35SS_SSC_PLL_FREQ1_FBDIV_MASK) 67 68 /* 69 * A35SSC A35SS_SSC_PLL_FREQ2 register 70 */ 71 #define A35SS_SSC_PLL_FREQ2_POSTDIV1_MASK GENMASK_32(2, 0) 72 #define A35SS_SSC_PLL_FREQ2_POSTDIV1_SHIFT U(0) 73 74 #define A35SS_SSC_PLL_FREQ2_POSTDIV2_MASK GENMASK_32(5, 3) 75 #define A35SS_SSC_PLL_FREQ2_POSTDIV2_SHIFT U(3) 76 77 #define A35SS_SSC_PLL_FREQ2_MASK GENMASK_32(5, 0) 78 79 /* 80 * A35SSC A35SS_SSC_PLL_EN register 81 */ 82 #define A35SS_SSC_PLL_ENABLE_PD_EN BIT(0) 83 #define A35SS_SSC_PLL_ENABLE_PD_MASK BIT(0) 84 85 #define A35SS_SSC_PLL_ENABLE_LOCKP_MASK BIT(1) 86 87 #define A35SS_SSC_PLL_ENABLE_NRESET_SWPLL_FF_EN BIT(2) 88 #define A35SS_SSC_PLL_ENABLE_NRESET_SWPLL_FF_MASK BIT(2) 89 90 /* 91 * Write masked value is SYSCONF register 92 * @id: SYSCONF register ID, processed with SYSCON_ID() macro 93 * @value: Value to be written 94 * @bitmsk: Bit mask applied to @value 95 */ 96 void stm32mp_syscfg_write(uint32_t id, uint32_t value, uint32_t bitmsk); 97 98 /* 99 * Read SYSCONF reagister 100 * @id: SYSCONF register ID, processed with SYSCON_ID() macro 101 */ 102 uint32_t stm32mp_syscfg_read(uint32_t id); 103 104 /* 105 * Set safe reset state 106 * @status: True to enable safe reset, false to disable safe reset 107 */ 108 void stm32mp25_syscfg_set_safe_reset(bool status); 109 110 #endif /*__STM32_SYSCONF_H__*/ 111