1PLATFORM_FLAVOR ?= ls1021atwr 2 3$(call force,CFG_GENERIC_BOOT,y) 4$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 5$(call force,CFG_GIC,y) 6$(call force,CFG_16550_UART,y) 7$(call force,CFG_PM_STUBS,y) 8$(call force,CFG_LS,y) 9 10$(call force,CFG_DRAM0_BASE,0x80000000) 11$(call force,CFG_TEE_OS_DRAM0_SIZE,0x4000000) 12 13ifeq ($(PLATFORM_FLAVOR),ls1021atwr) 14include core/arch/arm/cpu/cortex-a7.mk 15$(call force,CFG_TEE_CORE_NB_CORE,2) 16$(call force,CFG_DRAM0_SIZE,0x40000000) 17$(call force,CFG_CORE_CLUSTER_SHIFT,2) 18CFG_SHMEM_SIZE ?= 0x00100000 19CFG_BOOT_SYNC_CPU ?= y 20CFG_BOOT_SECONDARY_REQUEST ?= y 21endif 22 23ifeq ($(PLATFORM_FLAVOR),ls1021aqds) 24include core/arch/arm/cpu/cortex-a7.mk 25$(call force,CFG_TEE_CORE_NB_CORE,2) 26$(call force,CFG_DRAM0_SIZE,0x80000000) 27$(call force,CFG_CORE_CLUSTER_SHIFT,2) 28CFG_SHMEM_SIZE ?= 0x00100000 29CFG_BOOT_SYNC_CPU ?= y 30CFG_BOOT_SECONDARY_REQUEST ?= y 31endif 32 33ifeq ($(PLATFORM_FLAVOR),ls1012ardb) 34CFG_HW_UNQ_KEY_REQUEST ?= y 35include core/arch/arm/cpu/cortex-armv8-0.mk 36$(call force,CFG_TEE_CORE_NB_CORE,1) 37$(call force,CFG_DRAM0_SIZE,0x40000000) 38$(call force,CFG_CORE_CLUSTER_SHIFT,2) 39CFG_SHMEM_SIZE ?= 0x00200000 40endif 41 42ifeq ($(PLATFORM_FLAVOR),ls1012afrwy) 43CFG_HW_UNQ_KEY_REQUEST ?= y 44include core/arch/arm/cpu/cortex-armv8-0.mk 45$(call force,CFG_TEE_CORE_NB_CORE,1) 46$(call force,CFG_CORE_CLUSTER_SHIFT,2) 47CFG_DRAM0_SIZE ?= 0x20000000 48CFG_SHMEM_SIZE ?= 0x00200000 49endif 50 51ifeq ($(PLATFORM_FLAVOR),ls1043ardb) 52CFG_HW_UNQ_KEY_REQUEST ?= y 53include core/arch/arm/cpu/cortex-armv8-0.mk 54$(call force,CFG_TEE_CORE_NB_CORE,4) 55$(call force,CFG_DRAM0_SIZE,0x80000000) 56$(call force,CFG_CORE_CLUSTER_SHIFT,2) 57CFG_SHMEM_SIZE ?= 0x00200000 58endif 59 60ifeq ($(PLATFORM_FLAVOR),ls1046ardb) 61CFG_HW_UNQ_KEY_REQUEST ?= y 62include core/arch/arm/cpu/cortex-armv8-0.mk 63$(call force,CFG_CAAM_BIG_ENDIAN,y) 64$(call force,CFG_TEE_CORE_NB_CORE,4) 65$(call force,CFG_DRAM0_SIZE,0x80000000) 66$(call force,CFG_CORE_CLUSTER_SHIFT,2) 67CFG_SHMEM_SIZE ?= 0x00200000 68endif 69 70ifeq ($(PLATFORM_FLAVOR),ls1088ardb) 71CFG_HW_UNQ_KEY_REQUEST ?= y 72include core/arch/arm/cpu/cortex-armv8-0.mk 73$(call force,CFG_TEE_CORE_NB_CORE,8) 74$(call force,CFG_DRAM0_SIZE,0x80000000) 75$(call force,CFG_CORE_CLUSTER_SHIFT,2) 76$(call force,CFG_ARM_GICV3,y) 77CFG_SHMEM_SIZE ?= 0x00200000 78endif 79 80ifeq ($(PLATFORM_FLAVOR),ls2088ardb) 81CFG_HW_UNQ_KEY_REQUEST ?= y 82include core/arch/arm/cpu/cortex-armv8-0.mk 83$(call force,CFG_TEE_CORE_NB_CORE,8) 84$(call force,CFG_DRAM0_SIZE,0x80000000) 85$(call force,CFG_CORE_CLUSTER_SHIFT,1) 86$(call force,CFG_ARM_GICV3,y) 87CFG_SHMEM_SIZE ?= 0x00200000 88endif 89 90ifeq ($(PLATFORM_FLAVOR),lx2160ardb) 91CFG_HW_UNQ_KEY_REQUEST ?= y 92include core/arch/arm/cpu/cortex-armv8-0.mk 93$(call force,CFG_CAAM_LITTLE_ENDIAN,y) 94$(call force,CFG_TEE_CORE_NB_CORE,16) 95$(call force,CFG_DRAM0_SIZE,0x80000000) 96$(call force,CFG_CORE_CLUSTER_SHIFT,1) 97$(call force,CFG_ARM_GICV3,y) 98$(call force,CFG_PL011,y) 99CFG_SHMEM_SIZE ?= 0x00200000 100endif 101 102ifeq ($(PLATFORM_FLAVOR),ls1028ardb) 103CFG_HW_UNQ_KEY_REQUEST ?= y 104include core/arch/arm/cpu/cortex-armv8-0.mk 105$(call force,CFG_TEE_CORE_NB_CORE,2) 106$(call force,CFG_DRAM0_SIZE,0x80000000) 107$(call force,CFG_CORE_CLUSTER_SHIFT,1) 108$(call force,CFG_ARM_GICV3,y) 109CFG_SHMEM_SIZE ?= 0x00200000 110endif 111 112ifeq ($(platform-flavor-armv8),1) 113$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 114CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 115CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - CFG_SHMEM_SIZE) 116#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 117CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_SHMEM_SIZE) 118$(call force,CFG_ARM64_core,y) 119CFG_USER_TA_TARGETS ?= ta_arm64 120else 121#In ARMv7 platform CFG_SHMEM_SIZE is different to that of ARMv8 platforms. 122CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 123CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - (2*CFG_SHMEM_SIZE)) 124#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 125CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - (2*CFG_SHMEM_SIZE)) 126endif 127 128#Keeping Number of TEE thread equal to number of cores on the SoC 129CFG_NUM_THREADS ?= CFG_TEE_CORE_NB_CORE 130 131ifeq ($(CFG_ARM64_core),y) 132$(call force,CFG_WITH_LPAE,y) 133else 134$(call force,CFG_ARM32_core,y) 135$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 136endif 137 138CFG_CRYPTO_SIZE_OPTIMIZATION ?= n 139CFG_WITH_STACK_CANARIES ?= y 140 141# NXP CAAM support is not enabled by default and can be enabled 142# on the command line 143CFG_NXP_CAAM ?= n 144 145ifeq ($(CFG_NXP_CAAM),y) 146# If NXP CAAM Driver is supported, the Crypto Driver interfacing 147# it with generic crypto API can be enabled. 148CFG_CRYPTO_DRIVER ?= y 149CFG_CAAM_64BIT ?= y 150CFG_CRYPTO_DRIVER_DEBUG ?= n 151else 152$(call force,CFG_CRYPTO_DRIVER,n) 153$(call force,CFG_WITH_SOFTWARE_PRNG,y) 154endif 155 156# Cryptographic configuration 157include core/arch/arm/plat-ls/crypto_conf.mk 158