1PLATFORM_FLAVOR ?= ls1021atwr 2 3$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 4$(call force,CFG_GIC,y) 5$(call force,CFG_16550_UART,y) 6$(call force,CFG_LS,y) 7 8$(call force,CFG_DRAM0_BASE,0x80000000) 9$(call force,CFG_TEE_OS_DRAM0_SIZE,0x4000000) 10 11ifeq ($(PLATFORM_FLAVOR),ls1021atwr) 12include core/arch/arm/cpu/cortex-a7.mk 13$(call force,CFG_TEE_CORE_NB_CORE,2) 14$(call force,CFG_DRAM0_SIZE,0x40000000) 15$(call force,CFG_CORE_CLUSTER_SHIFT,2) 16CFG_SHMEM_SIZE ?= 0x00100000 17CFG_BOOT_SYNC_CPU ?= y 18CFG_BOOT_SECONDARY_REQUEST ?= y 19endif 20 21ifeq ($(PLATFORM_FLAVOR),ls1021aqds) 22include core/arch/arm/cpu/cortex-a7.mk 23$(call force,CFG_TEE_CORE_NB_CORE,2) 24$(call force,CFG_DRAM0_SIZE,0x80000000) 25$(call force,CFG_CORE_CLUSTER_SHIFT,2) 26CFG_SHMEM_SIZE ?= 0x00100000 27CFG_BOOT_SYNC_CPU ?= y 28CFG_BOOT_SECONDARY_REQUEST ?= y 29endif 30 31ifeq ($(PLATFORM_FLAVOR),ls1012ardb) 32include core/arch/arm/cpu/cortex-armv8-0.mk 33$(call force,CFG_TEE_CORE_NB_CORE,1) 34$(call force,CFG_DRAM0_SIZE,0x40000000) 35$(call force,CFG_CORE_CLUSTER_SHIFT,2) 36CFG_SHMEM_SIZE ?= 0x00200000 37endif 38 39ifeq ($(PLATFORM_FLAVOR),ls1012afrwy) 40include core/arch/arm/cpu/cortex-armv8-0.mk 41$(call force,CFG_TEE_CORE_NB_CORE,1) 42$(call force,CFG_CORE_CLUSTER_SHIFT,2) 43CFG_DRAM0_SIZE ?= 0x20000000 44CFG_SHMEM_SIZE ?= 0x00200000 45endif 46 47ifeq ($(PLATFORM_FLAVOR),ls1043ardb) 48include core/arch/arm/cpu/cortex-armv8-0.mk 49$(call force,CFG_TEE_CORE_NB_CORE,4) 50$(call force,CFG_DRAM0_SIZE,0x80000000) 51$(call force,CFG_CORE_CLUSTER_SHIFT,2) 52CFG_SHMEM_SIZE ?= 0x00200000 53endif 54 55ifeq ($(PLATFORM_FLAVOR),ls1046ardb) 56include core/arch/arm/cpu/cortex-armv8-0.mk 57$(call force,CFG_CAAM_BIG_ENDIAN,y) 58$(call force,CFG_TEE_CORE_NB_CORE,4) 59$(call force,CFG_DRAM0_SIZE,0x80000000) 60$(call force,CFG_CORE_CLUSTER_SHIFT,2) 61CFG_SHMEM_SIZE ?= 0x00200000 62endif 63 64ifeq ($(PLATFORM_FLAVOR),ls1088ardb) 65include core/arch/arm/cpu/cortex-armv8-0.mk 66$(call force,CFG_TEE_CORE_NB_CORE,8) 67$(call force,CFG_DRAM0_SIZE,0x80000000) 68$(call force,CFG_CORE_CLUSTER_SHIFT,2) 69$(call force,CFG_ARM_GICV3,y) 70CFG_SHMEM_SIZE ?= 0x00200000 71endif 72 73ifeq ($(PLATFORM_FLAVOR),ls2088ardb) 74include core/arch/arm/cpu/cortex-armv8-0.mk 75$(call force,CFG_TEE_CORE_NB_CORE,8) 76$(call force,CFG_DRAM0_SIZE,0x80000000) 77$(call force,CFG_CORE_CLUSTER_SHIFT,1) 78$(call force,CFG_ARM_GICV3,y) 79CFG_SHMEM_SIZE ?= 0x00200000 80endif 81 82ifeq ($(PLATFORM_FLAVOR),lx2160aqds) 83include core/arch/arm/cpu/cortex-armv8-0.mk 84$(call force,CFG_TEE_CORE_NB_CORE,16) 85$(call force,CFG_DRAM0_SIZE,0x80000000) 86$(call force,CFG_DRAM1_BASE,0x2080000000) 87$(call force,CFG_DRAM1_SIZE,0x1F80000000) 88$(call force,CFG_CORE_CLUSTER_SHIFT,1) 89$(call force,CFG_ARM_GICV3,y) 90$(call force,CFG_PL011,y) 91$(call force,CFG_CORE_ARM64_PA_BITS,48) 92$(call force,CFG_EMBED_DT,y) 93$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-qds.dts) 94CFG_LS_I2C ?= y 95CFG_LS_GPIO ?= y 96CFG_LS_DSPI ?= y 97CFG_SHMEM_SIZE ?= 0x00200000 98endif 99 100ifeq ($(PLATFORM_FLAVOR),lx2160ardb) 101include core/arch/arm/cpu/cortex-armv8-0.mk 102$(call force,CFG_CAAM_LITTLE_ENDIAN,y) 103$(call force,CFG_TEE_CORE_NB_CORE,16) 104$(call force,CFG_DRAM0_SIZE,0x80000000) 105$(call force,CFG_DRAM1_BASE,0x2080000000) 106$(call force,CFG_DRAM1_SIZE,0x1F80000000) 107$(call force,CFG_CORE_CLUSTER_SHIFT,1) 108$(call force,CFG_ARM_GICV3,y) 109$(call force,CFG_PL011,y) 110$(call force,CFG_CORE_ARM64_PA_BITS,48) 111$(call force,CFG_EMBED_DT,y) 112$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-rdb.dts) 113CFG_LS_I2C ?= y 114CFG_LS_GPIO ?= y 115CFG_LS_DSPI ?= y 116CFG_SHMEM_SIZE ?= 0x00200000 117endif 118 119ifeq ($(PLATFORM_FLAVOR),ls1028ardb) 120include core/arch/arm/cpu/cortex-armv8-0.mk 121$(call force,CFG_TEE_CORE_NB_CORE,2) 122$(call force,CFG_DRAM0_SIZE,0x80000000) 123$(call force,CFG_CORE_CLUSTER_SHIFT,1) 124$(call force,CFG_ARM_GICV3,y) 125CFG_SHMEM_SIZE ?= 0x00200000 126endif 127 128ifeq ($(platform-flavor-armv8),1) 129$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 130CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 131CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - CFG_SHMEM_SIZE) 132#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 133CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_SHMEM_SIZE) 134$(call force,CFG_ARM64_core,y) 135CFG_USER_TA_TARGETS ?= ta_arm64 136else 137#In ARMv7 platform CFG_SHMEM_SIZE is different to that of ARMv8 platforms. 138CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 139CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - (2*CFG_SHMEM_SIZE)) 140#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 141CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - (2*CFG_SHMEM_SIZE)) 142endif 143 144#Keeping Number of TEE thread equal to number of cores on the SoC 145CFG_NUM_THREADS ?= CFG_TEE_CORE_NB_CORE 146 147ifeq ($(CFG_ARM64_core),y) 148$(call force,CFG_WITH_LPAE,y) 149else 150$(call force,CFG_ARM32_core,y) 151$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 152endif 153 154CFG_CRYPTO_SIZE_OPTIMIZATION ?= n 155 156# NXP CAAM support is not enabled by default and can be enabled 157# on the command line 158CFG_NXP_CAAM ?= n 159 160ifeq ($(CFG_NXP_CAAM),y) 161# If NXP CAAM Driver is supported, the Crypto Driver interfacing 162# it with generic crypto API can be enabled. 163CFG_CRYPTO_DRIVER ?= y 164CFG_CRYPTO_DRIVER_DEBUG ?= 0 165else 166$(call force,CFG_CRYPTO_DRIVER,n) 167$(call force,CFG_WITH_SOFTWARE_PRNG,y) 168endif 169 170# Cryptographic configuration 171include core/arch/arm/plat-ls/crypto_conf.mk 172