1PLATFORM_FLAVOR ?= ls1012ardb 2 3$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 4$(call force,CFG_GIC,y) 5$(call force,CFG_16550_UART,y) 6$(call force,CFG_LS,y) 7 8$(call force,CFG_DRAM0_BASE,0x80000000) 9$(call force,CFG_TEE_OS_DRAM0_SIZE,0x4000000) 10 11ifeq ($(PLATFORM_FLAVOR),ls1021aqds) 12include core/arch/arm/cpu/cortex-a7.mk 13$(call force,CFG_TEE_CORE_NB_CORE,2) 14$(call force,CFG_DRAM0_SIZE,0x80000000) 15$(call force,CFG_CORE_CLUSTER_SHIFT,2) 16CFG_SHMEM_SIZE ?= 0x00100000 17CFG_BOOT_SYNC_CPU ?= y 18CFG_BOOT_SECONDARY_REQUEST ?= y 19endif 20 21ifeq ($(PLATFORM_FLAVOR),ls1012ardb) 22include core/arch/arm/cpu/cortex-armv8-0.mk 23$(call force,CFG_TEE_CORE_NB_CORE,1) 24$(call force,CFG_DRAM0_SIZE,0x40000000) 25$(call force,CFG_CORE_CLUSTER_SHIFT,2) 26CFG_NUM_THREADS ?= 2 27CFG_SHMEM_SIZE ?= 0x00200000 28endif 29 30ifeq ($(PLATFORM_FLAVOR),ls1043ardb) 31include core/arch/arm/cpu/cortex-armv8-0.mk 32$(call force,CFG_TEE_CORE_NB_CORE,4) 33$(call force,CFG_DRAM0_SIZE,0x80000000) 34$(call force,CFG_CORE_CLUSTER_SHIFT,2) 35CFG_SHMEM_SIZE ?= 0x00200000 36endif 37 38ifeq ($(PLATFORM_FLAVOR),ls1046ardb) 39include core/arch/arm/cpu/cortex-armv8-0.mk 40$(call force,CFG_TEE_CORE_NB_CORE,4) 41$(call force,CFG_DRAM0_SIZE,0x80000000) 42$(call force,CFG_CORE_CLUSTER_SHIFT,2) 43CFG_SHMEM_SIZE ?= 0x00200000 44endif 45 46ifeq ($(PLATFORM_FLAVOR),ls1088ardb) 47include core/arch/arm/cpu/cortex-armv8-0.mk 48$(call force,CFG_TEE_CORE_NB_CORE,8) 49$(call force,CFG_DRAM0_SIZE,0x80000000) 50$(call force,CFG_CORE_CLUSTER_SHIFT,2) 51$(call force,CFG_ARM_GICV3,y) 52CFG_SHMEM_SIZE ?= 0x00200000 53endif 54 55ifeq ($(PLATFORM_FLAVOR),ls2088ardb) 56include core/arch/arm/cpu/cortex-armv8-0.mk 57$(call force,CFG_TEE_CORE_NB_CORE,8) 58$(call force,CFG_DRAM0_SIZE,0x80000000) 59$(call force,CFG_CORE_CLUSTER_SHIFT,1) 60$(call force,CFG_ARM_GICV3,y) 61CFG_SHMEM_SIZE ?= 0x00200000 62endif 63 64ifeq ($(PLATFORM_FLAVOR),lx2160aqds) 65include core/arch/arm/cpu/cortex-armv8-0.mk 66$(call force,CFG_TEE_CORE_NB_CORE,16) 67$(call force,CFG_DRAM0_SIZE,0x80000000) 68$(call force,CFG_DRAM1_BASE,0x2080000000) 69$(call force,CFG_DRAM1_SIZE,0x1F80000000) 70$(call force,CFG_CORE_CLUSTER_SHIFT,1) 71$(call force,CFG_ARM_GICV3,y) 72$(call force,CFG_PL011,y) 73$(call force,CFG_CORE_ARM64_PA_BITS,48) 74$(call force,CFG_EMBED_DTB,y) 75$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-qds.dts) 76CFG_LS_I2C ?= y 77CFG_LS_GPIO ?= y 78CFG_LS_DSPI ?= y 79CFG_SHMEM_SIZE ?= 0x00200000 80endif 81 82ifeq ($(PLATFORM_FLAVOR),lx2160ardb) 83include core/arch/arm/cpu/cortex-armv8-0.mk 84$(call force,CFG_TEE_CORE_NB_CORE,16) 85$(call force,CFG_DRAM0_SIZE,0x80000000) 86$(call force,CFG_DRAM1_BASE,0x2080000000) 87$(call force,CFG_DRAM1_SIZE,0x1F80000000) 88$(call force,CFG_CORE_CLUSTER_SHIFT,1) 89$(call force,CFG_ARM_GICV3,y) 90$(call force,CFG_PL011,y) 91$(call force,CFG_CORE_ARM64_PA_BITS,48) 92$(call force,CFG_EMBED_DTB,y) 93$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-rdb.dts) 94CFG_LS_I2C ?= y 95CFG_LS_GPIO ?= y 96CFG_LS_DSPI ?= y 97CFG_SHMEM_SIZE ?= 0x00200000 98endif 99 100ifeq ($(PLATFORM_FLAVOR),ls1028ardb) 101include core/arch/arm/cpu/cortex-armv8-0.mk 102$(call force,CFG_TEE_CORE_NB_CORE,2) 103$(call force,CFG_DRAM0_SIZE,0x80000000) 104$(call force,CFG_CORE_CLUSTER_SHIFT,1) 105$(call force,CFG_ARM_GICV3,y) 106CFG_SHMEM_SIZE ?= 0x00200000 107endif 108 109ifeq ($(platform-flavor-armv8),1) 110$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 111CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 112CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - CFG_SHMEM_SIZE) 113#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 114CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_SHMEM_SIZE) 115$(call force,CFG_ARM64_core,y) 116CFG_USER_TA_TARGETS ?= ta_arm64 117else 118#In ARMv7 platform CFG_SHMEM_SIZE is different to that of ARMv8 platforms. 119CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 120CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - (2*CFG_SHMEM_SIZE)) 121#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 122CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - (2*CFG_SHMEM_SIZE)) 123endif 124 125#Keeping Number of TEE thread equal to number of cores on the SoC 126CFG_NUM_THREADS ?= $(CFG_TEE_CORE_NB_CORE) 127 128ifneq ($(CFG_ARM64_core),y) 129$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 130endif 131 132CFG_CRYPTO_SIZE_OPTIMIZATION ?= n 133 134# NXP CAAM support is not enabled by default and can be enabled 135# on the command line 136CFG_NXP_CAAM ?= n 137 138ifeq ($(CFG_NXP_CAAM),y) 139# If NXP CAAM Driver is supported, the Crypto Driver interfacing 140# it with generic crypto API can be enabled. 141CFG_CRYPTO_DRIVER ?= y 142CFG_CRYPTO_DRIVER_DEBUG ?= 0 143else 144$(call force,CFG_CRYPTO_DRIVER,n) 145$(call force,CFG_WITH_SOFTWARE_PRNG,y) 146endif 147 148# Cryptographic configuration 149include core/arch/arm/plat-ls/crypto_conf.mk 150