1PLATFORM_FLAVOR ?= ls1021atwr 2 3$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 4$(call force,CFG_GIC,y) 5$(call force,CFG_16550_UART,y) 6$(call force,CFG_LS,y) 7 8$(call force,CFG_DRAM0_BASE,0x80000000) 9$(call force,CFG_TEE_OS_DRAM0_SIZE,0x4000000) 10 11ifeq ($(PLATFORM_FLAVOR),ls1021atwr) 12include core/arch/arm/cpu/cortex-a7.mk 13$(call force,CFG_TEE_CORE_NB_CORE,2) 14$(call force,CFG_DRAM0_SIZE,0x40000000) 15$(call force,CFG_CORE_CLUSTER_SHIFT,2) 16CFG_SHMEM_SIZE ?= 0x00100000 17CFG_BOOT_SYNC_CPU ?= y 18CFG_BOOT_SECONDARY_REQUEST ?= y 19endif 20 21ifeq ($(PLATFORM_FLAVOR),ls1021aqds) 22include core/arch/arm/cpu/cortex-a7.mk 23$(call force,CFG_TEE_CORE_NB_CORE,2) 24$(call force,CFG_DRAM0_SIZE,0x80000000) 25$(call force,CFG_CORE_CLUSTER_SHIFT,2) 26CFG_SHMEM_SIZE ?= 0x00100000 27CFG_BOOT_SYNC_CPU ?= y 28CFG_BOOT_SECONDARY_REQUEST ?= y 29endif 30 31ifeq ($(PLATFORM_FLAVOR),ls1012ardb) 32CFG_HW_UNQ_KEY_REQUEST ?= y 33include core/arch/arm/cpu/cortex-armv8-0.mk 34$(call force,CFG_TEE_CORE_NB_CORE,1) 35$(call force,CFG_DRAM0_SIZE,0x40000000) 36$(call force,CFG_CORE_CLUSTER_SHIFT,2) 37CFG_SHMEM_SIZE ?= 0x00200000 38endif 39 40ifeq ($(PLATFORM_FLAVOR),ls1012afrwy) 41CFG_HW_UNQ_KEY_REQUEST ?= y 42include core/arch/arm/cpu/cortex-armv8-0.mk 43$(call force,CFG_TEE_CORE_NB_CORE,1) 44$(call force,CFG_CORE_CLUSTER_SHIFT,2) 45CFG_DRAM0_SIZE ?= 0x20000000 46CFG_SHMEM_SIZE ?= 0x00200000 47endif 48 49ifeq ($(PLATFORM_FLAVOR),ls1043ardb) 50CFG_HW_UNQ_KEY_REQUEST ?= y 51include core/arch/arm/cpu/cortex-armv8-0.mk 52$(call force,CFG_TEE_CORE_NB_CORE,4) 53$(call force,CFG_DRAM0_SIZE,0x80000000) 54$(call force,CFG_CORE_CLUSTER_SHIFT,2) 55CFG_SHMEM_SIZE ?= 0x00200000 56endif 57 58ifeq ($(PLATFORM_FLAVOR),ls1046ardb) 59CFG_HW_UNQ_KEY_REQUEST ?= y 60include core/arch/arm/cpu/cortex-armv8-0.mk 61$(call force,CFG_CAAM_BIG_ENDIAN,y) 62$(call force,CFG_TEE_CORE_NB_CORE,4) 63$(call force,CFG_DRAM0_SIZE,0x80000000) 64$(call force,CFG_CORE_CLUSTER_SHIFT,2) 65CFG_SHMEM_SIZE ?= 0x00200000 66endif 67 68ifeq ($(PLATFORM_FLAVOR),ls1088ardb) 69CFG_HW_UNQ_KEY_REQUEST ?= y 70include core/arch/arm/cpu/cortex-armv8-0.mk 71$(call force,CFG_TEE_CORE_NB_CORE,8) 72$(call force,CFG_DRAM0_SIZE,0x80000000) 73$(call force,CFG_CORE_CLUSTER_SHIFT,2) 74$(call force,CFG_ARM_GICV3,y) 75CFG_SHMEM_SIZE ?= 0x00200000 76endif 77 78ifeq ($(PLATFORM_FLAVOR),ls2088ardb) 79CFG_HW_UNQ_KEY_REQUEST ?= y 80include core/arch/arm/cpu/cortex-armv8-0.mk 81$(call force,CFG_TEE_CORE_NB_CORE,8) 82$(call force,CFG_DRAM0_SIZE,0x80000000) 83$(call force,CFG_CORE_CLUSTER_SHIFT,1) 84$(call force,CFG_ARM_GICV3,y) 85CFG_SHMEM_SIZE ?= 0x00200000 86endif 87 88ifeq ($(PLATFORM_FLAVOR),lx2160ardb) 89CFG_HW_UNQ_KEY_REQUEST ?= y 90include core/arch/arm/cpu/cortex-armv8-0.mk 91$(call force,CFG_CAAM_LITTLE_ENDIAN,y) 92$(call force,CFG_TEE_CORE_NB_CORE,16) 93$(call force,CFG_DRAM0_SIZE,0x80000000) 94$(call force,CFG_CORE_CLUSTER_SHIFT,1) 95$(call force,CFG_ARM_GICV3,y) 96$(call force,CFG_PL011,y) 97CFG_SHMEM_SIZE ?= 0x00200000 98endif 99 100ifeq ($(PLATFORM_FLAVOR),ls1028ardb) 101CFG_HW_UNQ_KEY_REQUEST ?= y 102include core/arch/arm/cpu/cortex-armv8-0.mk 103$(call force,CFG_TEE_CORE_NB_CORE,2) 104$(call force,CFG_DRAM0_SIZE,0x80000000) 105$(call force,CFG_CORE_CLUSTER_SHIFT,1) 106$(call force,CFG_ARM_GICV3,y) 107CFG_SHMEM_SIZE ?= 0x00200000 108endif 109 110ifeq ($(platform-flavor-armv8),1) 111$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 112CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 113CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - CFG_SHMEM_SIZE) 114#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 115CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_SHMEM_SIZE) 116$(call force,CFG_ARM64_core,y) 117CFG_USER_TA_TARGETS ?= ta_arm64 118else 119#In ARMv7 platform CFG_SHMEM_SIZE is different to that of ARMv8 platforms. 120CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 121CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - (2*CFG_SHMEM_SIZE)) 122#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 123CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - (2*CFG_SHMEM_SIZE)) 124endif 125 126#Keeping Number of TEE thread equal to number of cores on the SoC 127CFG_NUM_THREADS ?= CFG_TEE_CORE_NB_CORE 128 129ifeq ($(CFG_ARM64_core),y) 130$(call force,CFG_WITH_LPAE,y) 131else 132$(call force,CFG_ARM32_core,y) 133$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 134endif 135 136CFG_CRYPTO_SIZE_OPTIMIZATION ?= n 137 138# NXP CAAM support is not enabled by default and can be enabled 139# on the command line 140CFG_NXP_CAAM ?= n 141 142ifeq ($(CFG_NXP_CAAM),y) 143# If NXP CAAM Driver is supported, the Crypto Driver interfacing 144# it with generic crypto API can be enabled. 145CFG_CRYPTO_DRIVER ?= y 146CFG_CAAM_64BIT ?= y 147CFG_CRYPTO_DRIVER_DEBUG ?= n 148else 149$(call force,CFG_CRYPTO_DRIVER,n) 150$(call force,CFG_WITH_SOFTWARE_PRNG,y) 151endif 152 153# Cryptographic configuration 154include core/arch/arm/plat-ls/crypto_conf.mk 155