1PLATFORM_FLAVOR ?= ls1021atwr 2 3$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 4$(call force,CFG_GIC,y) 5$(call force,CFG_16550_UART,y) 6$(call force,CFG_LS,y) 7 8$(call force,CFG_DRAM0_BASE,0x80000000) 9$(call force,CFG_TEE_OS_DRAM0_SIZE,0x4000000) 10 11ifeq ($(PLATFORM_FLAVOR),ls1021atwr) 12include core/arch/arm/cpu/cortex-a7.mk 13$(call force,CFG_TEE_CORE_NB_CORE,2) 14$(call force,CFG_DRAM0_SIZE,0x40000000) 15$(call force,CFG_CORE_CLUSTER_SHIFT,2) 16CFG_SHMEM_SIZE ?= 0x00100000 17CFG_BOOT_SYNC_CPU ?= y 18CFG_BOOT_SECONDARY_REQUEST ?= y 19endif 20 21ifeq ($(PLATFORM_FLAVOR),ls1021aqds) 22include core/arch/arm/cpu/cortex-a7.mk 23$(call force,CFG_TEE_CORE_NB_CORE,2) 24$(call force,CFG_DRAM0_SIZE,0x80000000) 25$(call force,CFG_CORE_CLUSTER_SHIFT,2) 26CFG_SHMEM_SIZE ?= 0x00100000 27CFG_BOOT_SYNC_CPU ?= y 28CFG_BOOT_SECONDARY_REQUEST ?= y 29endif 30 31ifeq ($(PLATFORM_FLAVOR),ls1012ardb) 32CFG_HW_UNQ_KEY_REQUEST ?= y 33include core/arch/arm/cpu/cortex-armv8-0.mk 34$(call force,CFG_TEE_CORE_NB_CORE,1) 35$(call force,CFG_DRAM0_SIZE,0x40000000) 36$(call force,CFG_CORE_CLUSTER_SHIFT,2) 37CFG_SHMEM_SIZE ?= 0x00200000 38endif 39 40ifeq ($(PLATFORM_FLAVOR),ls1012afrwy) 41CFG_HW_UNQ_KEY_REQUEST ?= y 42include core/arch/arm/cpu/cortex-armv8-0.mk 43$(call force,CFG_TEE_CORE_NB_CORE,1) 44$(call force,CFG_CORE_CLUSTER_SHIFT,2) 45CFG_DRAM0_SIZE ?= 0x20000000 46CFG_SHMEM_SIZE ?= 0x00200000 47endif 48 49ifeq ($(PLATFORM_FLAVOR),ls1043ardb) 50CFG_HW_UNQ_KEY_REQUEST ?= y 51include core/arch/arm/cpu/cortex-armv8-0.mk 52$(call force,CFG_TEE_CORE_NB_CORE,4) 53$(call force,CFG_DRAM0_SIZE,0x80000000) 54$(call force,CFG_CORE_CLUSTER_SHIFT,2) 55CFG_SHMEM_SIZE ?= 0x00200000 56endif 57 58ifeq ($(PLATFORM_FLAVOR),ls1046ardb) 59CFG_HW_UNQ_KEY_REQUEST ?= y 60include core/arch/arm/cpu/cortex-armv8-0.mk 61$(call force,CFG_CAAM_BIG_ENDIAN,y) 62$(call force,CFG_TEE_CORE_NB_CORE,4) 63$(call force,CFG_DRAM0_SIZE,0x80000000) 64$(call force,CFG_CORE_CLUSTER_SHIFT,2) 65CFG_SHMEM_SIZE ?= 0x00200000 66endif 67 68ifeq ($(PLATFORM_FLAVOR),ls1088ardb) 69CFG_HW_UNQ_KEY_REQUEST ?= y 70include core/arch/arm/cpu/cortex-armv8-0.mk 71$(call force,CFG_TEE_CORE_NB_CORE,8) 72$(call force,CFG_DRAM0_SIZE,0x80000000) 73$(call force,CFG_CORE_CLUSTER_SHIFT,2) 74$(call force,CFG_ARM_GICV3,y) 75CFG_SHMEM_SIZE ?= 0x00200000 76endif 77 78ifeq ($(PLATFORM_FLAVOR),ls2088ardb) 79CFG_HW_UNQ_KEY_REQUEST ?= y 80include core/arch/arm/cpu/cortex-armv8-0.mk 81$(call force,CFG_TEE_CORE_NB_CORE,8) 82$(call force,CFG_DRAM0_SIZE,0x80000000) 83$(call force,CFG_CORE_CLUSTER_SHIFT,1) 84$(call force,CFG_ARM_GICV3,y) 85CFG_SHMEM_SIZE ?= 0x00200000 86endif 87 88ifeq ($(PLATFORM_FLAVOR),lx2160aqds) 89CFG_HW_UNQ_KEY_REQUEST ?= y 90include core/arch/arm/cpu/cortex-armv8-0.mk 91$(call force,CFG_TEE_CORE_NB_CORE,16) 92$(call force,CFG_DRAM0_SIZE,0x80000000) 93$(call force,CFG_DRAM1_BASE,0x2080000000) 94$(call force,CFG_DRAM1_SIZE,0x1F80000000) 95$(call force,CFG_CORE_CLUSTER_SHIFT,1) 96$(call force,CFG_ARM_GICV3,y) 97$(call force,CFG_PL011,y) 98$(call force,CFG_CORE_ARM64_PA_BITS,48) 99$(call force,CFG_EMBED_DT,y) 100$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-qds.dts) 101CFG_LS_I2C ?= y 102CFG_SHMEM_SIZE ?= 0x00200000 103endif 104 105ifeq ($(PLATFORM_FLAVOR),lx2160ardb) 106CFG_HW_UNQ_KEY_REQUEST ?= y 107include core/arch/arm/cpu/cortex-armv8-0.mk 108$(call force,CFG_CAAM_LITTLE_ENDIAN,y) 109$(call force,CFG_TEE_CORE_NB_CORE,16) 110$(call force,CFG_DRAM0_SIZE,0x80000000) 111$(call force,CFG_DRAM1_BASE,0x2080000000) 112$(call force,CFG_DRAM1_SIZE,0x1F80000000) 113$(call force,CFG_CORE_CLUSTER_SHIFT,1) 114$(call force,CFG_ARM_GICV3,y) 115$(call force,CFG_PL011,y) 116$(call force,CFG_CORE_ARM64_PA_BITS,48) 117$(call force,CFG_EMBED_DT,y) 118$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-rdb.dts) 119CFG_LS_I2C ?= y 120CFG_SHMEM_SIZE ?= 0x00200000 121endif 122 123ifeq ($(PLATFORM_FLAVOR),ls1028ardb) 124CFG_HW_UNQ_KEY_REQUEST ?= y 125include core/arch/arm/cpu/cortex-armv8-0.mk 126$(call force,CFG_TEE_CORE_NB_CORE,2) 127$(call force,CFG_DRAM0_SIZE,0x80000000) 128$(call force,CFG_CORE_CLUSTER_SHIFT,1) 129$(call force,CFG_ARM_GICV3,y) 130CFG_SHMEM_SIZE ?= 0x00200000 131endif 132 133ifeq ($(platform-flavor-armv8),1) 134$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 135CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 136CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - CFG_SHMEM_SIZE) 137#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 138CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_SHMEM_SIZE) 139$(call force,CFG_ARM64_core,y) 140CFG_USER_TA_TARGETS ?= ta_arm64 141else 142#In ARMv7 platform CFG_SHMEM_SIZE is different to that of ARMv8 platforms. 143CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 144CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - (2*CFG_SHMEM_SIZE)) 145#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 146CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - (2*CFG_SHMEM_SIZE)) 147endif 148 149#Keeping Number of TEE thread equal to number of cores on the SoC 150CFG_NUM_THREADS ?= CFG_TEE_CORE_NB_CORE 151 152ifeq ($(CFG_ARM64_core),y) 153$(call force,CFG_WITH_LPAE,y) 154else 155$(call force,CFG_ARM32_core,y) 156$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 157endif 158 159CFG_CRYPTO_SIZE_OPTIMIZATION ?= n 160 161# NXP CAAM support is not enabled by default and can be enabled 162# on the command line 163CFG_NXP_CAAM ?= n 164 165ifeq ($(CFG_NXP_CAAM),y) 166# If NXP CAAM Driver is supported, the Crypto Driver interfacing 167# it with generic crypto API can be enabled. 168CFG_CRYPTO_DRIVER ?= y 169CFG_CAAM_64BIT ?= y 170CFG_CRYPTO_DRIVER_DEBUG ?= n 171else 172$(call force,CFG_CRYPTO_DRIVER,n) 173$(call force,CFG_WITH_SOFTWARE_PRNG,y) 174endif 175 176# Cryptographic configuration 177include core/arch/arm/plat-ls/crypto_conf.mk 178