1PLATFORM_FLAVOR ?= ls1021atwr 2 3$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 4$(call force,CFG_GIC,y) 5$(call force,CFG_16550_UART,y) 6$(call force,CFG_PM_STUBS,y) 7$(call force,CFG_LS,y) 8 9$(call force,CFG_DRAM0_BASE,0x80000000) 10$(call force,CFG_TEE_OS_DRAM0_SIZE,0x4000000) 11 12ifeq ($(PLATFORM_FLAVOR),ls1021atwr) 13include core/arch/arm/cpu/cortex-a7.mk 14$(call force,CFG_TEE_CORE_NB_CORE,2) 15$(call force,CFG_DRAM0_SIZE,0x40000000) 16$(call force,CFG_CORE_CLUSTER_SHIFT,2) 17CFG_SHMEM_SIZE ?= 0x00100000 18CFG_BOOT_SYNC_CPU ?= y 19CFG_BOOT_SECONDARY_REQUEST ?= y 20endif 21 22ifeq ($(PLATFORM_FLAVOR),ls1021aqds) 23include core/arch/arm/cpu/cortex-a7.mk 24$(call force,CFG_TEE_CORE_NB_CORE,2) 25$(call force,CFG_DRAM0_SIZE,0x80000000) 26$(call force,CFG_CORE_CLUSTER_SHIFT,2) 27CFG_SHMEM_SIZE ?= 0x00100000 28CFG_BOOT_SYNC_CPU ?= y 29CFG_BOOT_SECONDARY_REQUEST ?= y 30endif 31 32ifeq ($(PLATFORM_FLAVOR),ls1012ardb) 33CFG_HW_UNQ_KEY_REQUEST ?= y 34include core/arch/arm/cpu/cortex-armv8-0.mk 35$(call force,CFG_TEE_CORE_NB_CORE,1) 36$(call force,CFG_DRAM0_SIZE,0x40000000) 37$(call force,CFG_CORE_CLUSTER_SHIFT,2) 38CFG_SHMEM_SIZE ?= 0x00200000 39endif 40 41ifeq ($(PLATFORM_FLAVOR),ls1012afrwy) 42CFG_HW_UNQ_KEY_REQUEST ?= y 43include core/arch/arm/cpu/cortex-armv8-0.mk 44$(call force,CFG_TEE_CORE_NB_CORE,1) 45$(call force,CFG_CORE_CLUSTER_SHIFT,2) 46CFG_DRAM0_SIZE ?= 0x20000000 47CFG_SHMEM_SIZE ?= 0x00200000 48endif 49 50ifeq ($(PLATFORM_FLAVOR),ls1043ardb) 51CFG_HW_UNQ_KEY_REQUEST ?= y 52include core/arch/arm/cpu/cortex-armv8-0.mk 53$(call force,CFG_TEE_CORE_NB_CORE,4) 54$(call force,CFG_DRAM0_SIZE,0x80000000) 55$(call force,CFG_CORE_CLUSTER_SHIFT,2) 56CFG_SHMEM_SIZE ?= 0x00200000 57endif 58 59ifeq ($(PLATFORM_FLAVOR),ls1046ardb) 60CFG_HW_UNQ_KEY_REQUEST ?= y 61include core/arch/arm/cpu/cortex-armv8-0.mk 62$(call force,CFG_CAAM_BIG_ENDIAN,y) 63$(call force,CFG_TEE_CORE_NB_CORE,4) 64$(call force,CFG_DRAM0_SIZE,0x80000000) 65$(call force,CFG_CORE_CLUSTER_SHIFT,2) 66CFG_SHMEM_SIZE ?= 0x00200000 67endif 68 69ifeq ($(PLATFORM_FLAVOR),ls1088ardb) 70CFG_HW_UNQ_KEY_REQUEST ?= y 71include core/arch/arm/cpu/cortex-armv8-0.mk 72$(call force,CFG_TEE_CORE_NB_CORE,8) 73$(call force,CFG_DRAM0_SIZE,0x80000000) 74$(call force,CFG_CORE_CLUSTER_SHIFT,2) 75$(call force,CFG_ARM_GICV3,y) 76CFG_SHMEM_SIZE ?= 0x00200000 77endif 78 79ifeq ($(PLATFORM_FLAVOR),ls2088ardb) 80CFG_HW_UNQ_KEY_REQUEST ?= y 81include core/arch/arm/cpu/cortex-armv8-0.mk 82$(call force,CFG_TEE_CORE_NB_CORE,8) 83$(call force,CFG_DRAM0_SIZE,0x80000000) 84$(call force,CFG_CORE_CLUSTER_SHIFT,1) 85$(call force,CFG_ARM_GICV3,y) 86CFG_SHMEM_SIZE ?= 0x00200000 87endif 88 89ifeq ($(PLATFORM_FLAVOR),lx2160ardb) 90CFG_HW_UNQ_KEY_REQUEST ?= y 91include core/arch/arm/cpu/cortex-armv8-0.mk 92$(call force,CFG_CAAM_LITTLE_ENDIAN,y) 93$(call force,CFG_TEE_CORE_NB_CORE,16) 94$(call force,CFG_DRAM0_SIZE,0x80000000) 95$(call force,CFG_CORE_CLUSTER_SHIFT,1) 96$(call force,CFG_ARM_GICV3,y) 97$(call force,CFG_PL011,y) 98CFG_SHMEM_SIZE ?= 0x00200000 99endif 100 101ifeq ($(PLATFORM_FLAVOR),ls1028ardb) 102CFG_HW_UNQ_KEY_REQUEST ?= y 103include core/arch/arm/cpu/cortex-armv8-0.mk 104$(call force,CFG_TEE_CORE_NB_CORE,2) 105$(call force,CFG_DRAM0_SIZE,0x80000000) 106$(call force,CFG_CORE_CLUSTER_SHIFT,1) 107$(call force,CFG_ARM_GICV3,y) 108CFG_SHMEM_SIZE ?= 0x00200000 109endif 110 111ifeq ($(platform-flavor-armv8),1) 112$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 113CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 114CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - CFG_SHMEM_SIZE) 115#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 116CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_SHMEM_SIZE) 117$(call force,CFG_ARM64_core,y) 118CFG_USER_TA_TARGETS ?= ta_arm64 119else 120#In ARMv7 platform CFG_SHMEM_SIZE is different to that of ARMv8 platforms. 121CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 122CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - (2*CFG_SHMEM_SIZE)) 123#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 124CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - (2*CFG_SHMEM_SIZE)) 125endif 126 127#Keeping Number of TEE thread equal to number of cores on the SoC 128CFG_NUM_THREADS ?= CFG_TEE_CORE_NB_CORE 129 130ifeq ($(CFG_ARM64_core),y) 131$(call force,CFG_WITH_LPAE,y) 132else 133$(call force,CFG_ARM32_core,y) 134$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 135endif 136 137CFG_CRYPTO_SIZE_OPTIMIZATION ?= n 138 139# NXP CAAM support is not enabled by default and can be enabled 140# on the command line 141CFG_NXP_CAAM ?= n 142 143ifeq ($(CFG_NXP_CAAM),y) 144# If NXP CAAM Driver is supported, the Crypto Driver interfacing 145# it with generic crypto API can be enabled. 146CFG_CRYPTO_DRIVER ?= y 147CFG_CAAM_64BIT ?= y 148CFG_CRYPTO_DRIVER_DEBUG ?= n 149else 150$(call force,CFG_CRYPTO_DRIVER,n) 151$(call force,CFG_WITH_SOFTWARE_PRNG,y) 152endif 153 154# Cryptographic configuration 155include core/arch/arm/plat-ls/crypto_conf.mk 156