1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/clock/stm32mp13-clksrc.h> 10#include <dt-bindings/firewall/stm32mp13-tzc400.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/gpio/stm32mp_gpio.h> 13#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 14#include "stm32mp135.dtsi" 15#include "stm32mp13xf.dtsi" 16#include "stm32mp13-pinctrl.dtsi" 17 18/ { 19 model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 20 compatible = "st,stm32mp135f-dk", "st,stm32mp135"; 21 22 aliases { 23 serial0 = &uart4; 24 serial1 = &usart1; 25 }; 26 27 chosen { 28 stdout-path = "serial0:115200n8"; 29 }; 30 31 memory@c0000000 { 32 device_type = "memory"; 33 reg = <0xc0000000 0x20000000>; 34 }; 35 36 reserved-memory { 37 #address-cells = <1>; 38 #size-cells = <1>; 39 ranges; 40 41 optee_framebuffer: optee-framebuffer@dd000000 { 42 /* Secure framebuffer memory */ 43 reg = <0xdd000000 0x1000000>; 44 st,protreg = <DT_TZC_REGION_S_RDWR 0>; 45 no-map; 46 }; 47 }; 48 49 vin: vin { 50 compatible = "regulator-fixed"; 51 regulator-name = "vin"; 52 regulator-min-microvolt = <5000000>; 53 regulator-max-microvolt = <5000000>; 54 regulator-always-on; 55 }; 56 57 v3v3_ao: v3v3_ao { 58 compatible = "regulator-fixed"; 59 regulator-name = "v3v3_ao"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 regulator-always-on; 63 }; 64}; 65 66&bsec { 67 board_id: board_id@f0 { 68 reg = <0xf0 0x4>; 69 st,non-secure-otp; 70 }; 71}; 72 73&etzpc { 74 st,decprot = 75 <DECPROT(STM32MP1_ETZPC_ADC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 76 <DECPROT(STM32MP1_ETZPC_ADC2_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 77 <DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 78 <DECPROT(STM32MP1_ETZPC_CRYP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 79 <DECPROT(STM32MP1_ETZPC_DCMIPP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 80 <DECPROT(STM32MP1_ETZPC_DDRCTRLPHY_ID, DECPROT_NS_R_S_W, DECPROT_UNLOCK)>, 81 <DECPROT(STM32MP1_ETZPC_ETH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 82 <DECPROT(STM32MP1_ETZPC_ETH2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 83 <DECPROT(STM32MP1_ETZPC_FMC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 84 <DECPROT(STM32MP1_ETZPC_HASH_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 85 <DECPROT(STM32MP1_ETZPC_I2C3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 86 <DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 87 <DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 88 <DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 89 <DECPROT(STM32MP1_ETZPC_LPTIM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 90 <DECPROT(STM32MP1_ETZPC_LPTIM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 91 <DECPROT(STM32MP1_ETZPC_LTDC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 92 <DECPROT(STM32MP1_ETZPC_MCE_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 93 <DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 94 <DECPROT(STM32MP1_ETZPC_PKA_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 95 <DECPROT(STM32MP1_ETZPC_QSPI_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 96 <DECPROT(STM32MP1_ETZPC_RNG_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 97 <DECPROT(STM32MP1_ETZPC_SAES_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 98 <DECPROT(STM32MP1_ETZPC_SDMMC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 99 <DECPROT(STM32MP1_ETZPC_SDMMC2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 100 <DECPROT(STM32MP1_ETZPC_SPI4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 101 <DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 102 <DECPROT(STM32MP1_ETZPC_SRAM1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 103 <DECPROT(STM32MP1_ETZPC_SRAM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 104 <DECPROT(STM32MP1_ETZPC_SRAM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 105 <DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 106 <DECPROT(STM32MP1_ETZPC_TIM12_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 107 <DECPROT(STM32MP1_ETZPC_TIM13_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 108 <DECPROT(STM32MP1_ETZPC_TIM14_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 109 <DECPROT(STM32MP1_ETZPC_TIM15_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 110 <DECPROT(STM32MP1_ETZPC_TIM16_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 111 <DECPROT(STM32MP1_ETZPC_TIM17_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 112 <DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 113 <DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 114 <DECPROT(STM32MP1_ETZPC_USBPHYCTRL_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 115 <DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>; 116}; 117 118&gpiob { 119 st,protreg = <TZPROT(9)>; 120}; 121 122&gpiod { 123 st,protreg = <TZPROT(7)>; 124}; 125 126&gpioe { 127 st,protreg = <TZPROT(15)>; 128}; 129 130&hash { 131 status = "okay"; 132}; 133 134&i2c4 { 135 pinctrl-names = "default"; 136 pinctrl-0 = <&i2c4_pins_a>; 137 i2c-scl-rising-time-ns = <185>; 138 i2c-scl-falling-time-ns = <20>; 139 clock-frequency = <400000>; 140 status = "okay"; 141 142 pmic: stpmic@33 { 143 compatible = "st,stpmic1"; 144 reg = <0x33>; 145 status = "okay"; 146 st,wakeup-pin-number = <1>; 147 st,notif-it-id = <0>; 148 149 regulators { 150 compatible = "st,stpmic1-regulators"; 151 buck1-supply = <&vin>; 152 buck2-supply = <&vin>; 153 buck3-supply = <&vin>; 154 buck4-supply = <&vin>; 155 ldo1-supply = <&vin>; 156 ldo4-supply = <&vin>; 157 ldo5-supply = <&vin>; 158 ldo6-supply = <&vin>; 159 vref_ddr-supply = <&vin>; 160 pwr_sw1-supply = <&bst_out>; 161 pwr_sw2-supply = <&v3v3_ao>; 162 163 vddcpu: buck1 { 164 regulator-name = "vddcpu"; 165 regulator-min-microvolt = <1250000>; 166 regulator-max-microvolt = <1350000>; 167 regulator-always-on; 168 regulator-over-current-protection; 169 170 lp-stop { 171 regulator-suspend-microvolt = <1250000>; 172 }; 173 lplv-stop { 174 regulator-suspend-microvolt = <900000>; 175 }; 176 lplv-stop2 { 177 regulator-off-in-suspend; 178 }; 179 standby-ddr-sr { 180 regulator-off-in-suspend; 181 }; 182 standby-ddr-off { 183 regulator-off-in-suspend; 184 }; 185 }; 186 187 vdd_ddr: buck2 { 188 regulator-name = "vdd_ddr"; 189 regulator-min-microvolt = <1350000>; 190 regulator-max-microvolt = <1350000>; 191 regulator-always-on; 192 regulator-over-current-protection; 193 194 standby-ddr-off { 195 regulator-off-in-suspend; 196 }; 197 }; 198 199 vdd: buck3 { 200 regulator-name = "vdd"; 201 regulator-min-microvolt = <3300000>; 202 regulator-max-microvolt = <3300000>; 203 regulator-always-on; 204 st,mask-reset; 205 regulator-over-current-protection; 206 }; 207 208 vddcore: buck4 { 209 regulator-name = "vddcore"; 210 regulator-min-microvolt = <1250000>; 211 regulator-max-microvolt = <1250000>; 212 regulator-always-on; 213 regulator-over-current-protection; 214 215 lplv-stop { 216 regulator-suspend-microvolt = <900000>; 217 }; 218 lplv-stop2 { 219 regulator-suspend-microvolt = <900000>; 220 }; 221 standby-ddr-sr { 222 regulator-off-in-suspend; 223 }; 224 standby-ddr-off { 225 regulator-off-in-suspend; 226 }; 227 }; 228 229 vdd_adc: ldo1 { 230 regulator-name = "vdd_adc"; 231 regulator-min-microvolt = <3300000>; 232 regulator-max-microvolt = <3300000>; 233 234 standby-ddr-sr { 235 regulator-off-in-suspend; 236 }; 237 standby-ddr-off { 238 regulator-off-in-suspend; 239 }; 240 }; 241 242 unused1: ldo2 { 243 regulator-name = "ldo2"; 244 }; 245 246 unused2: ldo3 { 247 regulator-name = "ldo3"; 248 }; 249 250 vdd_usb: ldo4 { 251 regulator-name = "vdd_usb"; 252 regulator-min-microvolt = <3300000>; 253 regulator-max-microvolt = <3300000>; 254 255 standby-ddr-sr { 256 regulator-off-in-suspend; 257 }; 258 standby-ddr-off { 259 regulator-off-in-suspend; 260 }; 261 }; 262 263 vdd_sd: ldo5 { 264 regulator-name = "vdd_sd"; 265 regulator-min-microvolt = <3300000>; 266 regulator-max-microvolt = <3300000>; 267 regulator-boot-on; 268 269 standby-ddr-sr { 270 regulator-off-in-suspend; 271 }; 272 standby-ddr-off { 273 regulator-off-in-suspend; 274 }; 275 }; 276 277 v1v8_periph: ldo6 { 278 regulator-name = "v1v8_periph"; 279 regulator-min-microvolt = <1800000>; 280 regulator-max-microvolt = <1800000>; 281 282 standby-ddr-sr { 283 regulator-off-in-suspend; 284 }; 285 standby-ddr-off { 286 regulator-off-in-suspend; 287 }; 288 }; 289 290 vref_ddr: vref_ddr { 291 regulator-name = "vref_ddr"; 292 regulator-always-on; 293 294 standby-ddr-sr { 295 regulator-off-in-suspend; 296 }; 297 standby-ddr-off { 298 regulator-off-in-suspend; 299 }; 300 }; 301 302 bst_out: boost { 303 regulator-name = "bst_out"; 304 }; 305 306 v3v3_sw: pwr_sw2 { 307 regulator-name = "v3v3_sw"; 308 regulator-active-discharge = <1>; 309 regulator-min-microvolt = <3300000>; 310 regulator-max-microvolt = <3300000>; 311 }; 312 }; 313 }; 314}; 315 316&iwdg1 { 317 timeout-sec = <32>; 318 status = "okay"; 319}; 320 321&oem_enc_key { 322 st,non-secure-otp-provisioning; 323}; 324 325&pka { 326 status = "okay"; 327}; 328 329&pwr_regulators { 330 vdd-supply = <&vdd>; 331 vdd_3v3_usbfs-supply = <&vdd_usb>; 332}; 333 334&rcc { 335 compatible = "st,stm32mp13-rcc", "syscon"; 336 337 st,clksrc = < 338 CLK_MPU_PLL1P 339 CLK_AXI_PLL2P 340 CLK_MLAHBS_PLL3 341 CLK_RTC_LSE 342 CLK_MCO1_HSE 343 CLK_MCO2_DISABLED 344 CLK_CKPER_HSE 345 CLK_ETH1_PLL4P 346 CLK_ETH2_PLL4P 347 CLK_SDMMC1_PLL4P 348 CLK_SDMMC2_PLL4P 349 CLK_STGEN_HSE 350 CLK_USBPHY_HSE 351 CLK_I2C4_HSI 352 CLK_I2C5_HSI 353 CLK_USBO_USBPHY 354 CLK_ADC2_CKPER 355 CLK_I2C12_HSI 356 CLK_UART1_HSI 357 CLK_UART2_HSI 358 CLK_UART35_HSI 359 CLK_UART4_HSI 360 CLK_UART6_HSI 361 CLK_UART78_HSI 362 CLK_SAES_AXI 363 CLK_DCMIPP_PLL2Q 364 CLK_LPTIM3_PCLK3 365 CLK_RNG1_PLL4R 366 >; 367 368 st,clkdiv = < 369 DIV(DIV_MPU, 1) 370 DIV(DIV_AXI, 0) 371 DIV(DIV_MLAHB, 0) 372 DIV(DIV_APB1, 1) 373 DIV(DIV_APB2, 1) 374 DIV(DIV_APB3, 1) 375 DIV(DIV_APB4, 1) 376 DIV(DIV_APB5, 2) 377 DIV(DIV_APB6, 1) 378 DIV(DIV_RTC, 0) 379 DIV(DIV_MCO1, 0) 380 DIV(DIV_MCO2, 0) 381 >; 382 383 st,pll_vco { 384 pll1_vco_2000Mhz: pll1-vco-2000Mhz { 385 src = <CLK_PLL12_HSE>; 386 divmn = <1 82>; 387 frac = <0xAAA>; 388 }; 389 390 pll1_vco_1300Mhz: pll1-vco-1300Mhz { 391 src = <CLK_PLL12_HSE>; 392 divmn = <2 80>; 393 frac = <0x800>; 394 }; 395 396 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 397 src = <CLK_PLL12_HSE>; 398 divmn = <2 65>; 399 frac = <0x1400>; 400 }; 401 402 pll3_vco_417Mhz: pll3-vco-417Mhz { 403 src = <CLK_PLL3_HSE>; 404 divmn = <1 33>; 405 frac = <0x1a04>; 406 }; 407 408 pll4_vco_600Mhz: pll4-vco-600Mhz { 409 src = <CLK_PLL4_HSE>; 410 divmn = <1 49>; 411 }; 412 }; 413 414 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 415 pll1: st,pll@0 { 416 compatible = "st,stm32mp1-pll"; 417 reg = <0>; 418 419 st,pll = <&pll1_cfg1>; 420 421 pll1_cfg1: pll1_cfg1 { 422 st,pll_vco = <&pll1_vco_1300Mhz>; 423 st,pll_div_pqr = <0 1 1>; 424 }; 425 426 pll1_cfg2: pll1_cfg2 { 427 st,pll_vco = <&pll1_vco_2000Mhz>; 428 st,pll_div_pqr = <0 1 1>; 429 }; 430 }; 431 432 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ 433 pll2: st,pll@1 { 434 compatible = "st,stm32mp1-pll"; 435 reg = <1>; 436 437 st,pll = <&pll2_cfg1>; 438 439 pll2_cfg1: pll2_cfg1 { 440 st,pll_vco = <&pll2_vco_1066Mhz>; 441 st,pll_div_pqr = <1 1 0>; 442 }; 443 }; 444 445 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 446 pll3: st,pll@2 { 447 compatible = "st,stm32mp1-pll"; 448 reg = <2>; 449 450 st,pll = <&pll3_cfg1>; 451 452 pll3_cfg1: pll3_cfg1 { 453 st,pll_vco = <&pll3_vco_417Mhz>; 454 st,pll_div_pqr = <1 16 36>; 455 }; 456 }; 457 458 /* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */ 459 pll4: st,pll@3 { 460 compatible = "st,stm32mp1-pll"; 461 reg = <3>; 462 st,pll = <&pll4_cfg1>; 463 464 pll4_cfg1: pll4_cfg1 { 465 st,pll_vco = <&pll4_vco_600Mhz>; 466 st,pll_div_pqr = <11 59 11>; 467 }; 468 }; 469 470 st,clk_opp { 471 /* CK_MPU clock config for MP13 */ 472 st,ck_mpu { 473 474 cfg_1 { 475 hz = <650000000>; 476 st,clksrc = <CLK_MPU_PLL1P>; 477 st,pll = <&pll1_cfg1>; 478 }; 479 480 cfg_2 { 481 hz = <1000000000>; 482 st,clksrc = <CLK_MPU_PLL1P>; 483 st,pll = <&pll1_cfg2>; 484 }; 485 }; 486 }; 487}; 488 489&rng { 490 status = "okay"; 491 clock-error-detect; 492}; 493 494&rtc { 495 status = "okay"; 496}; 497 498&saes { 499 status = "okay"; 500}; 501 502&sdmmc1_io { 503 vddsd1-supply = <&vdd>; 504}; 505 506&sdmmc2_io { 507 vddsd2-supply = <&vdd>; 508}; 509 510&tzc400 { 511 memory-region = <&optee_framebuffer>; 512}; 513 514&uart4 { 515 pinctrl-names = "default"; 516 pinctrl-0 = <&uart4_pins_a>; 517 status = "okay"; 518}; 519 520&usart1 { 521 pinctrl-names = "default"; 522 pinctrl-0 = <&usart1_pins_a>; 523 uart-has-rtscts; 524 status = "disabled"; 525}; 526