1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/clock/stm32mp13-clksrc.h> 10#include "stm32mp135.dtsi" 11#include "stm32mp13xf.dtsi" 12#include "stm32mp13-pinctrl.dtsi" 13 14/ { 15 model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 16 compatible = "st,stm32mp135f-dk", "st,stm32mp135"; 17 18 aliases { 19 serial0 = &uart4; 20 serial1 = &usart1; 21 }; 22 23 chosen { 24 stdout-path = "serial0:115200n8"; 25 }; 26 27 memory@c0000000 { 28 device_type = "memory"; 29 reg = <0xc0000000 0x20000000>; 30 }; 31 32 reserved-memory { 33 #address-cells = <1>; 34 #size-cells = <1>; 35 ranges; 36 37 optee_framebuffer: optee-framebuffer@dd000000 { 38 /* Secure framebuffer memory */ 39 reg = <0xdd000000 0x1000000>; 40 no-map; 41 }; 42 }; 43 44 vin: vin { 45 compatible = "regulator-fixed"; 46 regulator-name = "vin"; 47 regulator-min-microvolt = <5000000>; 48 regulator-max-microvolt = <5000000>; 49 regulator-always-on; 50 }; 51 52 v3v3_ao: v3v3_ao { 53 compatible = "regulator-fixed"; 54 regulator-name = "v3v3_ao"; 55 regulator-min-microvolt = <3300000>; 56 regulator-max-microvolt = <3300000>; 57 regulator-always-on; 58 }; 59}; 60 61&bsec { 62 board_id: board_id@f0 { 63 reg = <0xf0 0x4>; 64 st,non-secure-otp; 65 }; 66}; 67 68&rcc { 69 compatible = "st,stm32mp13-rcc", "syscon"; 70 71 st,clksrc = < 72 CLK_MPU_PLL1P 73 CLK_AXI_PLL2P 74 CLK_MLAHBS_PLL3 75 CLK_RTC_LSE 76 CLK_MCO1_HSE 77 CLK_MCO2_DISABLED 78 CLK_CKPER_HSE 79 CLK_ETH1_PLL4P 80 CLK_ETH2_PLL4P 81 CLK_SDMMC1_PLL4P 82 CLK_SDMMC2_PLL4P 83 CLK_STGEN_HSE 84 CLK_USBPHY_HSE 85 CLK_I2C4_HSI 86 CLK_USBO_USBPHY 87 CLK_ADC2_CKPER 88 CLK_I2C12_HSI 89 CLK_UART1_HSI 90 CLK_UART2_HSI 91 CLK_UART35_HSI 92 CLK_UART4_HSI 93 CLK_UART6_HSI 94 CLK_UART78_HSI 95 CLK_SAES_AXI 96 CLK_DCMIPP_PLL2Q 97 CLK_LPTIM3_PCLK3 98 CLK_RNG1_PLL4R 99 >; 100 101 st,clkdiv = < 102 DIV(DIV_MPU, 1) 103 DIV(DIV_AXI, 0) 104 DIV(DIV_MLAHB, 0) 105 DIV(DIV_APB1, 1) 106 DIV(DIV_APB2, 1) 107 DIV(DIV_APB3, 1) 108 DIV(DIV_APB4, 1) 109 DIV(DIV_APB5, 2) 110 DIV(DIV_APB6, 1) 111 DIV(DIV_RTC, 0) 112 DIV(DIV_MCO1, 0) 113 DIV(DIV_MCO2, 0) 114 >; 115 116 st,pll_vco { 117 pll1_vco_2000Mhz: pll1-vco-2000Mhz { 118 src = < CLK_PLL12_HSE >; 119 divmn = < 1 82 >; 120 frac = < 0xAAA >; 121 }; 122 123 pll1_vco_1300Mhz: pll1-vco-1300Mhz { 124 src = < CLK_PLL12_HSE >; 125 divmn = < 2 80 >; 126 frac = < 0x800 >; 127 }; 128 129 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 130 src = < CLK_PLL12_HSE >; 131 divmn = < 2 65 >; 132 frac = < 0x1400 >; 133 }; 134 135 pll3_vco_417_8Mhz: pll3-vco-417_8Mhz { 136 src = < CLK_PLL3_HSE >; 137 divmn = < 1 33 >; 138 frac = < 0x1a04 >; 139 }; 140 141 pll4_vco_600Mhz: pll4-vco-600Mhz { 142 src = < CLK_PLL4_HSE >; 143 divmn = < 1 49 >; 144 }; 145 }; 146 147 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 148 pll1: st,pll@0 { 149 compatible = "st,stm32mp1-pll"; 150 reg = <0>; 151 152 st,pll = < &pll1_cfg1 >; 153 154 pll1_cfg1: pll1_cfg1 { 155 st,pll_vco = < &pll1_vco_1300Mhz >; 156 st,pll_div_pqr = < 0 1 1 >; 157 }; 158 159 pll1_cfg2: pll1_cfg2 { 160 st,pll_vco = < &pll1_vco_2000Mhz >; 161 st,pll_div_pqr = < 0 1 1 >; 162 }; 163 }; 164 165 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ 166 pll2: st,pll@1 { 167 compatible = "st,stm32mp1-pll"; 168 reg = <1>; 169 170 st,pll = < &pll2_cfg1 >; 171 172 pll2_cfg1: pll2_cfg1 { 173 st,pll_vco = < &pll2_vco_1066Mhz >; 174 st,pll_div_pqr = < 1 1 0 >; 175 }; 176 }; 177 178 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 179 pll3: st,pll@2 { 180 compatible = "st,stm32mp1-pll"; 181 reg = <2>; 182 183 st,pll = < &pll3_cfg1 >; 184 185 pll3_cfg1: pll3_cfg1 { 186 st,pll_vco = < &pll3_vco_417_8Mhz >; 187 st,pll_div_pqr = < 1 16 36 >; 188 }; 189 }; 190 191 /* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */ 192 pll4: st,pll@3 { 193 compatible = "st,stm32mp1-pll"; 194 reg = <3>; 195 st,pll = < &pll4_cfg1 >; 196 197 pll4_cfg1: pll4_cfg1 { 198 st,pll_vco = < &pll4_vco_600Mhz >; 199 st,pll_div_pqr = < 11 59 11 >; 200 }; 201 }; 202 203 st,clk_opp { 204 /* CK_MPU clock config for MP13 */ 205 st,ck_mpu { 206 207 cfg_1 { 208 hz = < 1000000000 >; 209 st,clksrc = < CLK_MPU_PLL1P >; 210 st,pll = < &pll1_cfg2 >; 211 }; 212 213 cfg_2 { 214 hz = < 650000000 >; 215 st,clksrc = < CLK_MPU_PLL1P >; 216 st,pll = < &pll1_cfg1 >; 217 }; 218 }; 219 }; 220}; 221 222&uart4 { 223 pinctrl-names = "default"; 224 pinctrl-0 = <&uart4_pins_a>; 225 status = "okay"; 226}; 227 228&usart1 { 229 pinctrl-names = "default"; 230 pinctrl-0 = <&usart1_pins_a>; 231 uart-has-rtscts; 232 status = "disabled"; 233}; 234 235&uart8 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&uart8_pins_a>; 238 status = "disabled"; 239}; 240