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Searched refs:VOP_LSB_DMA1 (Results 1 – 14 of 14) sorted by relevance

/utopia/UTPA2-700.0.x/modules/mvop/hal/maserati/mvop/
H A DhalMVOP.c3146 HAL_WriteByte(VOP_LSB_DMA1, 0x00); in HAL_MVOP_ResetReg()
3250 HAL_WriteByte(SUB_REG(VOP_LSB_DMA1), 0x00); in HAL_MVOP_ResetReg()
3756 regval = HAL_ReadRegBit(SUB_REG(VOP_LSB_DMA1), VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
3762 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
3779 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
H A DregMVOP.h184 #define VOP_LSB_DMA1 (MVOP_REG_BASE + 0x2D) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/macan/mvop/
H A DhalMVOP.c3068 HAL_WriteByte(VOP_LSB_DMA1, 0x00); in HAL_MVOP_ResetReg()
3168 HAL_WriteByte(SUB_REG(VOP_LSB_DMA1), 0x00); in HAL_MVOP_ResetReg()
3632 regval = HAL_ReadRegBit(SUB_REG(VOP_LSB_DMA1), VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
3638 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
3655 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
H A DregMVOP.h183 #define VOP_LSB_DMA1 (MVOP_REG_BASE + 0x2D) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/M7821/mvop/
H A DhalMVOP.c3123 HAL_WriteByte(VOP_LSB_DMA1, 0x00); in HAL_MVOP_ResetReg()
3223 HAL_WriteByte(SUB_REG(VOP_LSB_DMA1), 0x00); in HAL_MVOP_ResetReg()
3726 regval = HAL_ReadRegBit(SUB_REG(VOP_LSB_DMA1), VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
3732 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
3749 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
H A DregMVOP.h183 #define VOP_LSB_DMA1 (MVOP_REG_BASE + 0x2D) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/maxim/mvop/
H A DhalMVOP.c3214 HAL_WriteByte(VOP_LSB_DMA1, 0x00); in HAL_MVOP_ResetReg()
3328 HAL_WriteByte(SUB_REG(VOP_LSB_DMA1), 0x00); in HAL_MVOP_ResetReg()
3841 regval = HAL_ReadRegBit(SUB_REG(VOP_LSB_DMA1), VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
3847 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
3864 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
H A DregMVOP.h185 #define VOP_LSB_DMA1 (MVOP_REG_BASE + 0x2D) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/mooney/mvop/
H A DregMVOP.h185 #define VOP_LSB_DMA1 (MVOP_REG_BASE + 0x2D) macro
H A DhalMVOP.c2996 HAL_WriteByte(VOP_LSB_DMA1, 0x07); in HAL_MVOP_ResetReg()
3097 HAL_WriteByte(SUB_REG(VOP_LSB_DMA1), 0x07); in HAL_MVOP_ResetReg()
/utopia/UTPA2-700.0.x/modules/mvop/hal/M7621/mvop/
H A DregMVOP.h185 #define VOP_LSB_DMA1 (MVOP_REG_BASE + 0x2D) macro
H A DhalMVOP.c3780 regval = HAL_ReadRegBit(SUB_REG(VOP_LSB_DMA1), VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
3786 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
3803 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
/utopia/UTPA2-700.0.x/modules/mvop/hal/k7u/mvop/
H A DregMVOP.h189 #define VOP_LSB_DMA1 (MVOP_REG_BASE + 0x2D) macro
H A DhalMVOP.c3938 regval = HAL_ReadRegBit(SUB_REG(VOP_LSB_DMA1), VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
3944 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()
3961 HAL_WriteRegBit(SUB_REG(VOP_LSB_DMA1), bEnable, VOP_SYNC_2_DC_TIMING); in HAL_MVOP_Enable2DCTimingSync()