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Searched refs:TSP_TSP0_REG (Results 1 – 13 of 13) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/tee/
H A DhalTSP_tee.c115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2)))) macro
140 TSP_TSP0_REG(REG_TSP0_FW_DMA_ADDR_L) = ((MS_U16)u32FwAddr) & 0xFFFF; in HAL_TSP_Tee_Set_FWBuf()
142 TSP_TSP0_REG(REG_TSP0_FW_DMA_NUM) = (MS_U16)u32FwSize; in HAL_TSP_Tee_Set_FWBuf()
203 TSP_TSP0_REG(REG_TSP0_PVR_HEAD1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
204 TSP_TSP0_REG(REG_TSP0_PVR_HEAD1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
206 TSP_TSP0_REG(REG_TSP0_PVR_TAIL1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
207 TSP_TSP0_REG(REG_TSP0_PVR_TAIL1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
210 TSP_TSP0_REG(REG_TSP0_PVR_HEAD2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
211 TSP_TSP0_REG(REG_TSP0_PVR_HEAD2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
213 TSP_TSP0_REG(REG_TSP0_PVR_TAIL2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/tee/
H A DhalTSP_tee.c115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2)))) macro
140 TSP_TSP0_REG(REG_TSP0_FW_DMA_ADDR_L) = ((MS_U16)u32FwAddr) & 0xFFFF; in HAL_TSP_Tee_Set_FWBuf()
142 TSP_TSP0_REG(REG_TSP0_FW_DMA_NUM) = (MS_U16)u32FwSize; in HAL_TSP_Tee_Set_FWBuf()
203 TSP_TSP0_REG(REG_TSP0_PVR_HEAD1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
204 TSP_TSP0_REG(REG_TSP0_PVR_HEAD1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
206 TSP_TSP0_REG(REG_TSP0_PVR_TAIL1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
207 TSP_TSP0_REG(REG_TSP0_PVR_TAIL1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
210 TSP_TSP0_REG(REG_TSP0_PVR_HEAD2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
211 TSP_TSP0_REG(REG_TSP0_PVR_HEAD2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
213 TSP_TSP0_REG(REG_TSP0_PVR_TAIL2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/tee/
H A DhalTSP_tee.c115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2)))) macro
140 TSP_TSP0_REG(REG_TSP0_FW_DMA_ADDR_L) = ((MS_U16)u32FwAddr) & 0xFFFF; in HAL_TSP_Tee_Set_FWBuf()
142 TSP_TSP0_REG(REG_TSP0_FW_DMA_NUM) = (MS_U16)u32FwSize; in HAL_TSP_Tee_Set_FWBuf()
203 TSP_TSP0_REG(REG_TSP0_PVR_HEAD1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
204 TSP_TSP0_REG(REG_TSP0_PVR_HEAD1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
206 TSP_TSP0_REG(REG_TSP0_PVR_TAIL1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
207 TSP_TSP0_REG(REG_TSP0_PVR_TAIL1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
210 TSP_TSP0_REG(REG_TSP0_PVR_HEAD2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
211 TSP_TSP0_REG(REG_TSP0_PVR_HEAD2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
213 TSP_TSP0_REG(REG_TSP0_PVR_TAIL2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/tee/
H A DhalTSP_tee.c115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2)))) macro
140 TSP_TSP0_REG(REG_TSP0_FW_DMA_ADDR_L) = ((MS_U16)u32FwAddr) & 0xFFFF; in HAL_TSP_Tee_Set_FWBuf()
142 TSP_TSP0_REG(REG_TSP0_FW_DMA_NUM) = (MS_U16)u32FwSize; in HAL_TSP_Tee_Set_FWBuf()
203 TSP_TSP0_REG(REG_TSP0_PVR_HEAD1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
204 TSP_TSP0_REG(REG_TSP0_PVR_HEAD1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
206 TSP_TSP0_REG(REG_TSP0_PVR_TAIL1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
207 TSP_TSP0_REG(REG_TSP0_PVR_TAIL1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
210 TSP_TSP0_REG(REG_TSP0_PVR_HEAD2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
211 TSP_TSP0_REG(REG_TSP0_PVR_HEAD2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
213 TSP_TSP0_REG(REG_TSP0_PVR_TAIL2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/tee/
H A DhalTSP_tee.c115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2)))) macro
140 TSP_TSP0_REG(REG_TSP0_FW_DMA_ADDR_L) = ((MS_U16)u32FwAddr) & 0xFFFF; in HAL_TSP_Tee_Set_FWBuf()
142 TSP_TSP0_REG(REG_TSP0_FW_DMA_NUM) = (MS_U16)u32FwSize; in HAL_TSP_Tee_Set_FWBuf()
203 TSP_TSP0_REG(REG_TSP0_PVR_HEAD1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
204 TSP_TSP0_REG(REG_TSP0_PVR_HEAD1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
206 TSP_TSP0_REG(REG_TSP0_PVR_TAIL1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
207 TSP_TSP0_REG(REG_TSP0_PVR_TAIL1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
210 TSP_TSP0_REG(REG_TSP0_PVR_HEAD2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
211 TSP_TSP0_REG(REG_TSP0_PVR_HEAD2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
213 TSP_TSP0_REG(REG_TSP0_PVR_TAIL2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/tee/
H A DhalTSP_tee.c115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2)))) macro
141 TSP_TSP0_REG(REG_TSP0_FW_DMA_ADDR_L) = ((MS_U16)u32FwAddr) & 0xFFFF; in HAL_TSP_Tee_Set_FWBuf()
143 TSP_TSP0_REG(REG_TSP0_FW_DMA_NUM) = (MS_U16)u32FwSize; in HAL_TSP_Tee_Set_FWBuf()
205 TSP_TSP0_REG(REG_TSP0_PVR1_HEAD1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
206 TSP_TSP0_REG(REG_TSP0_PVR1_HEAD1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
208 TSP_TSP0_REG(REG_TSP0_PVR1_TAIL1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
209 TSP_TSP0_REG(REG_TSP0_PVR1_TAIL1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
212 TSP_TSP0_REG(REG_TSP0_PVR1_HEAD2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
213 TSP_TSP0_REG(REG_TSP0_PVR1_HEAD2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
215 TSP_TSP0_REG(REG_TSP0_PVR1_TAIL2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/tee/
H A DhalTSP_tee.c115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2)))) macro
141 TSP_TSP0_REG(REG_TSP0_FW_DMA_ADDR_L) = ((MS_U16)u32FwAddr) & 0xFFFF; in HAL_TSP_Tee_Set_FWBuf()
143 TSP_TSP0_REG(REG_TSP0_FW_DMA_NUM) = (MS_U16)u32FwSize; in HAL_TSP_Tee_Set_FWBuf()
205 TSP_TSP0_REG(REG_TSP0_PVR1_HEAD1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
206 TSP_TSP0_REG(REG_TSP0_PVR1_HEAD1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
208 TSP_TSP0_REG(REG_TSP0_PVR1_TAIL1_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
209 TSP_TSP0_REG(REG_TSP0_PVR1_TAIL1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
212 TSP_TSP0_REG(REG_TSP0_PVR1_HEAD2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
213 TSP_TSP0_REG(REG_TSP0_PVR1_HEAD2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
215 TSP_TSP0_REG(REG_TSP0_PVR1_TAIL2_L) = (MS_U16)(phyMiuAddr & 0xFFFF); in HAL_TSP_Tee_Set_PvrBuf()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c196 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2… macro
5503 _u16TSP0RegArray[u32ii] = TSP_TSP0_REG(u32ii); in HAL_TSP_SaveRegs()
5553 TSP_TSP0_REG(0x01) = _u16TSP0RegArray[0x01]; in HAL_TSP_RestoreRegs()
5554 TSP_TSP0_REG(0x02) = _u16TSP0RegArray[0x02]; in HAL_TSP_RestoreRegs()
5555 TSP_TSP0_REG(0x05) = _u16TSP0RegArray[0x05]; in HAL_TSP_RestoreRegs()
5556 TSP_TSP0_REG(0x06) = _u16TSP0RegArray[0x06]; in HAL_TSP_RestoreRegs()
5557 TSP_TSP0_REG(0x0e) |= (_u16TSP0RegArray[0x0e] & ~0x0058); //disable pvr2 record in HAL_TSP_RestoreRegs()
5558 TSP_TSP0_REG(0x0f) |= (_u16TSP0RegArray[0x0f] & ~0xC000); in HAL_TSP_RestoreRegs()
5559 TSP_TSP0_REG(0x12) = _u16TSP0RegArray[0x12]; in HAL_TSP_RestoreRegs()
5560 TSP_TSP0_REG(0x13) = _u16TSP0RegArray[0x13]; in HAL_TSP_RestoreRegs()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c197 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2… macro
5855 _u16TSP0RegArray[u32ii] = TSP_TSP0_REG(u32ii); in HAL_TSP_SaveRegs()
5893 TSP_TSP0_REG(0x01) = _u16TSP0RegArray[0x01]; in HAL_TSP_RestoreRegs()
5894 TSP_TSP0_REG(0x02) = _u16TSP0RegArray[0x02]; in HAL_TSP_RestoreRegs()
5895 TSP_TSP0_REG(0x05) = _u16TSP0RegArray[0x05]; in HAL_TSP_RestoreRegs()
5896 TSP_TSP0_REG(0x06) = _u16TSP0RegArray[0x06]; in HAL_TSP_RestoreRegs()
5897 TSP_TSP0_REG(0x0e) |= (_u16TSP0RegArray[0x0e] & ~0x0058); //disable pvr2 record in HAL_TSP_RestoreRegs()
5898 TSP_TSP0_REG(0x0f) |= (_u16TSP0RegArray[0x0f] & ~0xC000); in HAL_TSP_RestoreRegs()
5899 TSP_TSP0_REG(0x12) = _u16TSP0RegArray[0x12]; in HAL_TSP_RestoreRegs()
5900 TSP_TSP0_REG(0x13) = _u16TSP0RegArray[0x13]; in HAL_TSP_RestoreRegs()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c200 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2… macro
6279 _u16TSP0RegArray[u32ii] = TSP_TSP0_REG(u32ii); in HAL_TSP_SaveRegs()
6329 TSP_TSP0_REG(0x01) = _u16TSP0RegArray[0x01]; in HAL_TSP_RestoreRegs()
6330 TSP_TSP0_REG(0x02) = _u16TSP0RegArray[0x02]; in HAL_TSP_RestoreRegs()
6331 TSP_TSP0_REG(0x05) = _u16TSP0RegArray[0x05]; in HAL_TSP_RestoreRegs()
6332 TSP_TSP0_REG(0x06) = _u16TSP0RegArray[0x06]; in HAL_TSP_RestoreRegs()
6333 TSP_TSP0_REG(0x0e) |= (_u16TSP0RegArray[0x0e] & ~0x0058); //disable pvr2 record in HAL_TSP_RestoreRegs()
6334 TSP_TSP0_REG(0x0f) |= (_u16TSP0RegArray[0x0f] & ~0xC000); in HAL_TSP_RestoreRegs()
6335 TSP_TSP0_REG(0x12) = _u16TSP0RegArray[0x12]; in HAL_TSP_RestoreRegs()
6336 TSP_TSP0_REG(0x13) = _u16TSP0RegArray[0x13]; in HAL_TSP_RestoreRegs()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c200 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2… macro
6262 _u16TSP0RegArray[u32ii] = TSP_TSP0_REG(u32ii); in HAL_TSP_SaveRegs()
6312 TSP_TSP0_REG(0x01) = _u16TSP0RegArray[0x01]; in HAL_TSP_RestoreRegs()
6313 TSP_TSP0_REG(0x02) = _u16TSP0RegArray[0x02]; in HAL_TSP_RestoreRegs()
6314 TSP_TSP0_REG(0x05) = _u16TSP0RegArray[0x05]; in HAL_TSP_RestoreRegs()
6315 TSP_TSP0_REG(0x06) = _u16TSP0RegArray[0x06]; in HAL_TSP_RestoreRegs()
6316 TSP_TSP0_REG(0x0e) |= (_u16TSP0RegArray[0x0e] & ~0x0058); //disable pvr2 record in HAL_TSP_RestoreRegs()
6317 TSP_TSP0_REG(0x0f) |= (_u16TSP0RegArray[0x0f] & ~0xC000); in HAL_TSP_RestoreRegs()
6318 TSP_TSP0_REG(0x12) = _u16TSP0RegArray[0x12]; in HAL_TSP_RestoreRegs()
6319 TSP_TSP0_REG(0x13) = _u16TSP0RegArray[0x13]; in HAL_TSP_RestoreRegs()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c200 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2… macro
6336 _u16TSP0RegArray[u32ii] = TSP_TSP0_REG(u32ii); in HAL_TSP_SaveRegs()
6386 TSP_TSP0_REG(0x01) = _u16TSP0RegArray[0x01]; in HAL_TSP_RestoreRegs()
6387 TSP_TSP0_REG(0x02) = _u16TSP0RegArray[0x02]; in HAL_TSP_RestoreRegs()
6388 TSP_TSP0_REG(0x05) = _u16TSP0RegArray[0x05]; in HAL_TSP_RestoreRegs()
6389 TSP_TSP0_REG(0x06) = _u16TSP0RegArray[0x06]; in HAL_TSP_RestoreRegs()
6390 TSP_TSP0_REG(0x0e) |= (_u16TSP0RegArray[0x0e] & ~0x0058); //disable pvr2 record in HAL_TSP_RestoreRegs()
6391 TSP_TSP0_REG(0x0f) |= (_u16TSP0RegArray[0x0f] & ~0xC000); in HAL_TSP_RestoreRegs()
6392 TSP_TSP0_REG(0x12) = _u16TSP0RegArray[0x12]; in HAL_TSP_RestoreRegs()
6393 TSP_TSP0_REG(0x13) = _u16TSP0RegArray[0x13]; in HAL_TSP_RestoreRegs()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c200 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + REG_CTRL_BASE + ((addr)<<2… macro
6297 _u16TSP0RegArray[u32ii] = TSP_TSP0_REG(u32ii); in HAL_TSP_SaveRegs()
6347 TSP_TSP0_REG(0x01) = _u16TSP0RegArray[0x01]; in HAL_TSP_RestoreRegs()
6348 TSP_TSP0_REG(0x02) = _u16TSP0RegArray[0x02]; in HAL_TSP_RestoreRegs()
6349 TSP_TSP0_REG(0x05) = _u16TSP0RegArray[0x05]; in HAL_TSP_RestoreRegs()
6350 TSP_TSP0_REG(0x06) = _u16TSP0RegArray[0x06]; in HAL_TSP_RestoreRegs()
6351 TSP_TSP0_REG(0x0e) |= (_u16TSP0RegArray[0x0e] & ~0x0058); //disable pvr2 record in HAL_TSP_RestoreRegs()
6352 TSP_TSP0_REG(0x0f) |= (_u16TSP0RegArray[0x0f] & ~0xC000); in HAL_TSP_RestoreRegs()
6353 TSP_TSP0_REG(0x12) = _u16TSP0RegArray[0x12]; in HAL_TSP_RestoreRegs()
6354 TSP_TSP0_REG(0x13) = _u16TSP0RegArray[0x13]; in HAL_TSP_RestoreRegs()
[all …]