Searched refs:TSP_SEM_MIPS (Results 1 – 11 of 11) sorted by relevance
346 #define TSP_SEM_MIPS (_virtRegBase+ 0xC1488UL) // TSP_HW_SEMAPHORE2, TS3 0x22 macro351 REG16_T(TSP_SEM_MIPS) = 0; in HAL_TSP_HW_Lock_Init()366 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()377 REG16_T(TSP_SEM_MIPS) = 0xFFFF; in _HAL_TSP_HW_TryLock()405 REG16_T(TSP_SEM_MIPS) = 0x00; in _HAL_TSP_HW_Unlock()412 REG16_T(TSP_SEM_MIPS) = 0x00; in HAL_TSP_HW_Lock_Release()433 if (REG16_T(TSP_SEM_MIPS)) in HAL_TSP_TTX_IsAccess()454 #undef TSP_SEM_MIPS
350 #define TSP_SEM_MIPS (_virtRegBase+ 0xC1488UL) // TSP_HW_SEMAPHORE2, TS3 0x22 macro355 REG16_T(TSP_SEM_MIPS) = 0; in HAL_TSP_HW_Lock_Init()370 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()381 REG16_T(TSP_SEM_MIPS) = 0xFFFF; in _HAL_TSP_HW_TryLock()409 REG16_T(TSP_SEM_MIPS) = 0x00; in _HAL_TSP_HW_Unlock()416 REG16_T(TSP_SEM_MIPS) = 0x00; in HAL_TSP_HW_Lock_Release()437 if (REG16_T(TSP_SEM_MIPS)) in HAL_TSP_TTX_IsAccess()458 #undef TSP_SEM_MIPS
347 #define TSP_SEM_MIPS (_virtRegBase+ 0xC1488UL) // TSP_HW_SEMAPHORE2, TS3 0x22 macro352 REG16_T(TSP_SEM_MIPS) = 0; in HAL_TSP_HW_Lock_Init()367 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()378 REG16_T(TSP_SEM_MIPS) = 0xFFFF; in _HAL_TSP_HW_TryLock()406 REG16_T(TSP_SEM_MIPS) = 0x00; in _HAL_TSP_HW_Unlock()413 REG16_T(TSP_SEM_MIPS) = 0x00; in HAL_TSP_HW_Lock_Release()434 if (REG16_T(TSP_SEM_MIPS)) in HAL_TSP_TTX_IsAccess()455 #undef TSP_SEM_MIPS
424 #define TSP_SEM_MIPS (_u32RegBase+ 0xC1488) // sw_mail_box2 macro429 REG16_T(TSP_SEM_MIPS) = 0; in HAL_TSP_HW_Lock_Init()444 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()455 REG16_T(TSP_SEM_MIPS) = 0xFFFF; in _HAL_TSP_HW_TryLock()483 REG16_T(TSP_SEM_MIPS) = 0x00; in _HAL_TSP_HW_Unlock()490 REG16_T(TSP_SEM_MIPS) = 0x00; in HAL_TSP_HW_Lock_Release()511 if (REG16_T(TSP_SEM_MIPS)) in HAL_TSP_TTX_IsAccess()532 #undef TSP_SEM_MIPS
542 #define TSP_SEM_MIPS (_virtRegBase+ 0x2b5cUL) // sw_mail_box2 macro547 REG16_T(TSP_SEM_MIPS) = 0; in HAL_TSP_HW_Lock_Init()562 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()573 REG16_T(TSP_SEM_MIPS) = 0xFFFF; in _HAL_TSP_HW_TryLock()601 REG16_T(TSP_SEM_MIPS) = 0x00; in _HAL_TSP_HW_Unlock()608 REG16_T(TSP_SEM_MIPS) = 0x00; in HAL_TSP_HW_Lock_Release()629 if (REG16_T(TSP_SEM_MIPS)) in HAL_TSP_TTX_IsAccess()650 #undef TSP_SEM_MIPS
556 #define TSP_SEM_MIPS (_virtRegBase+ 0x2b5cUL) // sw_mail_box2 macro561 REG16_T(TSP_SEM_MIPS) = 0; in HAL_TSP_HW_Lock_Init()576 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()587 REG16_T(TSP_SEM_MIPS) = 0xFFFF; in _HAL_TSP_HW_TryLock()615 REG16_T(TSP_SEM_MIPS) = 0x00; in _HAL_TSP_HW_Unlock()622 REG16_T(TSP_SEM_MIPS) = 0x00; in HAL_TSP_HW_Lock_Release()643 if (REG16_T(TSP_SEM_MIPS)) in HAL_TSP_TTX_IsAccess()664 #undef TSP_SEM_MIPS
493 #define TSP_SEM_MIPS (_virtRegBase+ 0x2b5cUL) // sw_mail_box2 macro498 REG16_T(TSP_SEM_MIPS) = 0; in HAL_TSP_HW_Lock_Init()513 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()524 REG16_T(TSP_SEM_MIPS) = 0xFFFF; in _HAL_TSP_HW_TryLock()552 REG16_T(TSP_SEM_MIPS) = 0x00; in _HAL_TSP_HW_Unlock()559 REG16_T(TSP_SEM_MIPS) = 0x00; in HAL_TSP_HW_Lock_Release()580 if (REG16_T(TSP_SEM_MIPS)) in HAL_TSP_TTX_IsAccess()601 #undef TSP_SEM_MIPS
562 #define TSP_SEM_MIPS (_virtRegBase+ 0x2b5cUL) // sw_mail_box2 macro567 REG16_T(TSP_SEM_MIPS) = 0; in HAL_TSP_HW_Lock_Init()582 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()593 REG16_T(TSP_SEM_MIPS) = 0xFFFF; in _HAL_TSP_HW_TryLock()621 REG16_T(TSP_SEM_MIPS) = 0x00; in _HAL_TSP_HW_Unlock()628 REG16_T(TSP_SEM_MIPS) = 0x00; in HAL_TSP_HW_Lock_Release()649 if (REG16_T(TSP_SEM_MIPS)) in HAL_TSP_TTX_IsAccess()670 #undef TSP_SEM_MIPS
580 #define TSP_SEM_MIPS (_virtRegBase+ 0x2b5cUL) // sw_mail_box2 macro585 REG16_T(TSP_SEM_MIPS) = 0; in HAL_TSP_HW_Lock_Init()600 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS)) in _HAL_TSP_HW_TryLock()611 REG16_T(TSP_SEM_MIPS) = 0xFFFF; in _HAL_TSP_HW_TryLock()639 REG16_T(TSP_SEM_MIPS) = 0x00; in _HAL_TSP_HW_Unlock()646 REG16_T(TSP_SEM_MIPS) = 0x00; in HAL_TSP_HW_Lock_Release()667 if (REG16_T(TSP_SEM_MIPS)) in HAL_TSP_TTX_IsAccess()688 #undef TSP_SEM_MIPS