Searched refs:TSP_SEM_AEON (Results 1 – 11 of 11) sorted by relevance
344 #define TSP_SEM_AEON (_virtRegBase+ 0xC1480UL) //TSP_HW_SEMAPHORE0, TS3 0x20 macro350 REG16_T(TSP_SEM_AEON) = 0; in HAL_TSP_HW_Lock_Init()363 REG16_T(TSP_SEM_AEON) = 0xFFFF; in _HAL_TSP_HW_TryLock()380 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()401 REG16_T(TSP_SEM_AEON) = 0x00; in _HAL_TSP_HW_Unlock()411 REG16_T(TSP_SEM_AEON) = 0x00; in HAL_TSP_HW_Lock_Release()426 if ( REG16_T(TSP_SEM_AEON)) in HAL_TSP_TTX_IsAccess()453 #undef TSP_SEM_AEON
348 #define TSP_SEM_AEON (_virtRegBase+ 0xC1480UL) //TSP_HW_SEMAPHORE0, TS3 0x20 macro354 REG16_T(TSP_SEM_AEON) = 0; in HAL_TSP_HW_Lock_Init()367 REG16_T(TSP_SEM_AEON) = 0xFFFF; in _HAL_TSP_HW_TryLock()384 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()405 REG16_T(TSP_SEM_AEON) = 0x00; in _HAL_TSP_HW_Unlock()415 REG16_T(TSP_SEM_AEON) = 0x00; in HAL_TSP_HW_Lock_Release()430 if ( REG16_T(TSP_SEM_AEON)) in HAL_TSP_TTX_IsAccess()457 #undef TSP_SEM_AEON
345 #define TSP_SEM_AEON (_virtRegBase+ 0xC1480UL) //TSP_HW_SEMAPHORE0, TS3 0x20 macro351 REG16_T(TSP_SEM_AEON) = 0; in HAL_TSP_HW_Lock_Init()364 REG16_T(TSP_SEM_AEON) = 0xFFFF; in _HAL_TSP_HW_TryLock()381 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()402 REG16_T(TSP_SEM_AEON) = 0x00; in _HAL_TSP_HW_Unlock()412 REG16_T(TSP_SEM_AEON) = 0x00; in HAL_TSP_HW_Lock_Release()427 if ( REG16_T(TSP_SEM_AEON)) in HAL_TSP_TTX_IsAccess()454 #undef TSP_SEM_AEON
422 #define TSP_SEM_AEON (_u32RegBase+ 0xC1480) //sw_mail_box0 macro428 REG16_T(TSP_SEM_AEON) = 0; in HAL_TSP_HW_Lock_Init()441 REG16_T(TSP_SEM_AEON) = 0xFFFF; in _HAL_TSP_HW_TryLock()458 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()479 REG16_T(TSP_SEM_AEON) = 0x00; in _HAL_TSP_HW_Unlock()489 REG16_T(TSP_SEM_AEON) = 0x00; in HAL_TSP_HW_Lock_Release()504 if ( REG16_T(TSP_SEM_AEON)) in HAL_TSP_TTX_IsAccess()531 #undef TSP_SEM_AEON
540 #define TSP_SEM_AEON (_virtRegBase+ 0x2a34UL) //sw_mail_box0 macro546 REG16_T(TSP_SEM_AEON) = 0; in HAL_TSP_HW_Lock_Init()559 REG16_T(TSP_SEM_AEON) = 0xFFFF; in _HAL_TSP_HW_TryLock()576 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()597 REG16_T(TSP_SEM_AEON) = 0x00; in _HAL_TSP_HW_Unlock()607 REG16_T(TSP_SEM_AEON) = 0x00; in HAL_TSP_HW_Lock_Release()622 if ( REG16_T(TSP_SEM_AEON)) in HAL_TSP_TTX_IsAccess()649 #undef TSP_SEM_AEON
554 #define TSP_SEM_AEON (_virtRegBase+ 0x2a34UL) //sw_mail_box0 macro560 REG16_T(TSP_SEM_AEON) = 0; in HAL_TSP_HW_Lock_Init()573 REG16_T(TSP_SEM_AEON) = 0xFFFF; in _HAL_TSP_HW_TryLock()590 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()611 REG16_T(TSP_SEM_AEON) = 0x00; in _HAL_TSP_HW_Unlock()621 REG16_T(TSP_SEM_AEON) = 0x00; in HAL_TSP_HW_Lock_Release()636 if ( REG16_T(TSP_SEM_AEON)) in HAL_TSP_TTX_IsAccess()663 #undef TSP_SEM_AEON
491 #define TSP_SEM_AEON (_virtRegBase+ 0x2a34UL) //sw_mail_box0 macro497 REG16_T(TSP_SEM_AEON) = 0; in HAL_TSP_HW_Lock_Init()510 REG16_T(TSP_SEM_AEON) = 0xFFFF; in _HAL_TSP_HW_TryLock()527 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()548 REG16_T(TSP_SEM_AEON) = 0x00; in _HAL_TSP_HW_Unlock()558 REG16_T(TSP_SEM_AEON) = 0x00; in HAL_TSP_HW_Lock_Release()573 if ( REG16_T(TSP_SEM_AEON)) in HAL_TSP_TTX_IsAccess()600 #undef TSP_SEM_AEON
560 #define TSP_SEM_AEON (_virtRegBase+ 0x2a34UL) //sw_mail_box0 macro566 REG16_T(TSP_SEM_AEON) = 0; in HAL_TSP_HW_Lock_Init()579 REG16_T(TSP_SEM_AEON) = 0xFFFF; in _HAL_TSP_HW_TryLock()596 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()617 REG16_T(TSP_SEM_AEON) = 0x00; in _HAL_TSP_HW_Unlock()627 REG16_T(TSP_SEM_AEON) = 0x00; in HAL_TSP_HW_Lock_Release()642 if ( REG16_T(TSP_SEM_AEON)) in HAL_TSP_TTX_IsAccess()669 #undef TSP_SEM_AEON
578 #define TSP_SEM_AEON (_virtRegBase+ 0x2a34UL) //sw_mail_box0 macro584 REG16_T(TSP_SEM_AEON) = 0; in HAL_TSP_HW_Lock_Init()597 REG16_T(TSP_SEM_AEON) = 0xFFFF; in _HAL_TSP_HW_TryLock()614 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON))) in _HAL_TSP_HW_TryLock()635 REG16_T(TSP_SEM_AEON) = 0x00; in _HAL_TSP_HW_Unlock()645 REG16_T(TSP_SEM_AEON) = 0x00; in HAL_TSP_HW_Lock_Release()660 if ( REG16_T(TSP_SEM_AEON)) in HAL_TSP_TTX_IsAccess()687 #undef TSP_SEM_AEON