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Searched refs:TOP_CKG_VPU_DIS (Results 1 – 25 of 130) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/vpu/
H A DhalVPU.c255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
H A DregVPU.h337 #define TOP_CKG_VPU_DIS BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/vpu/
H A DhalVPU.c255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
H A DregVPU.h337 #define TOP_CKG_VPU_DIS BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/vpu/
H A DhalVPU.c255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/vpu/
H A DhalVPU.c255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
H A DregVPU.h337 #define TOP_CKG_VPU_DIS BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/vpu/
H A DhalVPU.c255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/vpu/
H A DhalVPU.c255 _VPU_WriteWordMask( REG_TOP_VPU , 0 , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
259 _VPU_WriteWordMask( REG_TOP_VPU , TOP_CKG_VPU_DIS , TOP_CKG_VPU_DIS ); in HAL_VPU_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/vpu_ex/
H A DhalVPU_EX.c1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
H A DregVPU_EX.h344 #define TOP_CKG_VPU_DIS BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/vpu_ex/
H A DhalVPU_EX.c1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
H A DregVPU_EX.h344 #define TOP_CKG_VPU_DIS BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/vpu_ex/
H A DhalVPU_EX.c1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
H A DregVPU_EX.h344 #define TOP_CKG_VPU_DIS BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/vpu_ex/
H A DhalVPU_EX.c1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
H A DregVPU_EX.h344 #define TOP_CKG_VPU_DIS BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/vpu_ex/
H A DhalVPU_EX.c1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/vpu_ex/
H A DhalVPU_EX.c1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
H A DregVPU_EX.h344 #define TOP_CKG_VPU_DIS BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/vpu_ex/
H A DhalVPU_EX.c1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/vpu_ex/
H A DhalVPU_EX.c1824 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1829 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
H A DregVPU_EX.h344 #define TOP_CKG_VPU_DIS BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/vpu_ex/
H A DhalVPU_EX.c1855 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1860 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/vpu_ex/
H A DhalVPU_EX.c1855 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()
1860 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS); in HAL_VPU_EX_PowerCtrl()

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