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Searched refs:TIMER_1_MAX_REG (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/wdt/drv/wdt/
H A DdrvWDT.c687 HAL_WDT_Write4Byte(TIMER_1_MAX_REG,u32count); in _MDrv_TIMER_Trigger()
876 HAL_WDT_Write4Byte(TIMER_1_MAX_REG, u32MaxTimer); in MDrv_TIMER_SetMaxMatch_U2K()
906 return (HAL_WDT_Read4Byte(TIMER_1_MAX_REG)); in MDrv_TIMER_GetMaxMatch_U2K()
/utopia/UTPA2-700.0.x/modules/wdt/hal/kano/wdt/
H A DregWDT.h136 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/manhattan/wdt/
H A DregWDT.h136 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/M7821/wdt/
H A DregWDT.h136 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/maxim/wdt/
H A DregWDT.h136 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/mainz/wdt/
H A DregWDT.h113 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/maserati/wdt/
H A DregWDT.h136 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/curry/wdt/
H A DregWDT.h136 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/k6lite/wdt/
H A DregWDT.h136 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/messi/wdt/
H A DregWDT.h113 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/maldives/wdt/
H A DregWDT.h113 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/mustang/wdt/
H A DregWDT.h113 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/k6/wdt/
H A DregWDT.h136 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/mooney/wdt/
H A DregWDT.h113 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/M7621/wdt/
H A DregWDT.h136 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/macan/wdt/
H A DregWDT.h136 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 macro