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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regWDT.h 98 /// @brief Piu Watch Dog Timer Registers Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_WDT_H_ 103 #define _REG_WDT_H_ 104 105 //////////////////////////////////////////////////////////////////////////////// 106 // Macro and Define 107 //////////////////////////////////////////////////////////////////////////////// 108 109 #define REG_WDT_BASE ( 0x3000UL ) 110 #define REG_TIMER0_BASE ( 0x3020UL ) 111 #define REG_TIMER1_BASE ( 0x3040UL ) 112 113 #define REG_WDT_SET(x) ( REG_WDT_BASE + 2*x ) 114 #define REG_TIMER0_SET(x) ( REG_TIMER0_BASE + 2*x ) 115 #define REG_TIMER1_SET(x) ( REG_TIMER1_BASE + 2*x ) 116 117 118 // WDT 119 #define REG_WDT_CLR REG_WDT_SET(0x00UL) 120 #define REG_WDT_RST REG_WDT_SET(0x02UL) 121 #define REG_WDT_INT REG_WDT_SET(0x03UL) 122 #define REG_WDT_MAX REG_WDT_SET(0x04UL) 123 #define REG_WDT_MAX2 REG_WDT_SET(0x05UL) 124 125 #define WDT_CLR_RESET_FLAG BIT(0) 126 #define WDT_RST BIT(0) 127 128 // Timer0 129 #define TIMER_0_CTRL_REG REG_TIMER0_SET(0x00UL) 130 #define TIMER_0_MATCH_REG REG_TIMER0_SET(0x01UL) //BIT0, RO 131 #define TIMER_0_MAX_REG REG_TIMER0_SET(0x02UL) //BIT0-BIT31 132 #define TIMER_0_COUNT_REG REG_TIMER0_SET(0x04UL) //BIT0-BIT31, RO 133 // Timer1 134 #define TIMER_1_CTRL_REG REG_TIMER1_SET(0x00UL) 135 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO 136 #define TIMER_1_MAX_REG REG_TIMER1_SET(0x02UL) //BIT0-BIT31 137 #define TIMER_1_COUNT_REG REG_TIMER1_SET(0x04UL) //BIT0-BIT31, RO 138 139 #define TIMER_ENABLE BIT(0) //(from 0 to max, then rolled) 140 #define TIMER_TRIGGER BIT(1) //(from 0 to max, then stop) 141 #define TIMER_DISABLE BITS(1:0,0) 142 #define TIMER_INTEN BIT(0) //BIT8 143 #define TIMER_MATCH BIT(0) 144 //////////////////////////////////////////////////////////////////////////////// 145 // Type and Structure 146 //////////////////////////////////////////////////////////////////////////////// 147 148 #endif // _REG_WDT_H_ 149