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Searched refs:TIMER_1_MATCH_REG (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/wdt/drv/wdt/
H A DdrvWDT.c705 HAL_WDT_WriteByte(TIMER_1_MATCH_REG,HAL_WDT_ReadByte(TIMER_1_MATCH_REG)|(TIMER_MATCH)); in MDrv_TIMER_Stop()
810 return (HAL_WDT_ReadByte(TIMER_1_MATCH_REG)&TIMER_MATCH); in MDrv_TIMER_HitMaxMatch_U2K()
/utopia/UTPA2-700.0.x/modules/wdt/hal/kano/wdt/
H A DregWDT.h135 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/manhattan/wdt/
H A DregWDT.h135 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/M7821/wdt/
H A DregWDT.h135 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/maxim/wdt/
H A DregWDT.h135 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/mainz/wdt/
H A DregWDT.h112 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/maserati/wdt/
H A DregWDT.h135 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/curry/wdt/
H A DregWDT.h135 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/k6lite/wdt/
H A DregWDT.h135 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/messi/wdt/
H A DregWDT.h112 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/maldives/wdt/
H A DregWDT.h112 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/mustang/wdt/
H A DregWDT.h112 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/k6/wdt/
H A DregWDT.h135 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/mooney/wdt/
H A DregWDT.h112 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/M7621/wdt/
H A DregWDT.h135 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro
/utopia/UTPA2-700.0.x/modules/wdt/hal/macan/wdt/
H A DregWDT.h135 #define TIMER_1_MATCH_REG REG_TIMER1_SET(0x01UL) //BIT0, RO macro