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Searched refs:SVD_REG_BASE (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v1/hal/maserati/jpd/
H A DregJPD.h185 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF
186 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08))
187 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A))
192 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15))
193 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F))
208 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17))
209 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18))
210 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19))
211 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A))
213 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B))
[all …]
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v1/hal/M7821/jpd/
H A DregJPD.h185 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF
186 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08))
187 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A))
192 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15))
193 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F))
208 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17))
209 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18))
210 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19))
211 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A))
213 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B))
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/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v1/hal/maxim/jpd/
H A DregJPD.h185 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF
186 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08))
187 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A))
192 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15))
193 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F))
208 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17))
209 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18))
210 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19))
211 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A))
213 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B))
[all …]
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v1/hal/manhattan/jpd/
H A DregJPD.h185 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF
186 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08))
187 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A))
192 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15))
193 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F))
208 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17))
209 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18))
210 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19))
211 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A))
213 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B))
[all …]
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v1/hal/M7621/jpd/
H A DregJPD.h185 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF
186 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08))
187 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A))
192 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15))
193 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F))
208 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17))
209 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18))
210 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19))
211 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A))
213 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B))
[all …]
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v1/hal/macan/jpd/
H A DregJPD.h185 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF
186 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08))
187 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A))
192 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15))
193 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F))
208 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17))
209 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18))
210 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19))
211 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A))
213 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B))
[all …]
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v2/hal/M7621/jpd_ex/
H A DregJPD.h225 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF
226 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08))
227 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A))
232 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15))
233 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F))
248 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17))
249 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18))
250 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19))
251 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A))
253 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B))
[all …]
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v2/hal/manhattan/jpd_ex/
H A DregJPD.h225 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF
226 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08))
227 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A))
232 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15))
233 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F))
248 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17))
249 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18))
250 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19))
251 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A))
253 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B))
[all …]
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v2/hal/maserati/jpd_ex/
H A DregJPD.h225 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF
226 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08))
227 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A))
232 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15))
233 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F))
248 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17))
249 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18))
250 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19))
251 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A))
253 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B))
[all …]
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v2/hal/maxim/jpd_ex/
H A DregJPD.h225 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF
226 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08))
227 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A))
232 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15))
233 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F))
248 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17))
249 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18))
250 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19))
251 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A))
253 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B))
[all …]
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v2/hal/M7821/jpd_ex/
H A DregJPD.h225 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF
226 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08))
227 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A))
232 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15))
233 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F))
248 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17))
249 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18))
250 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19))
251 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A))
253 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B))
[all …]
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v2/hal/macan/jpd_ex/
H A DregJPD.h225 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF
226 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08))
227 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A))
232 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15))
233 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F))
248 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17))
249 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18))
250 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19))
251 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A))
253 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B))
[all …]
/utopia/UTPA2-700.0.x/modules/pws/hal/maxim/pws/
H A DregPWS.h140 #define SVD_REG_BASE (0x1B00UL) // 0x1B00 - 0x1BFF macro
141 #define REG_SVD_SW_RST ( SVD_REG_BASE + 0X0A*2 )
/utopia/UTPA2-700.0.x/modules/pws/hal/M7621/pws/
H A DregPWS.h140 #define SVD_REG_BASE (0x1B00UL) // 0x1B00 - 0x1BFF macro
141 #define REG_SVD_SW_RST ( SVD_REG_BASE + 0X0A*2 )
/utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/
H A DregPWS.h140 #define SVD_REG_BASE (0x1B00UL) // 0x1B00 - 0x1BFF macro
141 #define REG_SVD_SW_RST ( SVD_REG_BASE + 0X0A*2 )
/utopia/UTPA2-700.0.x/modules/pws/hal/mustang/pws/
H A DregPWS.h125 #define SVD_REG_BASE (0x1B00) // 0x1B00 - 0x1BFF macro
126 #define REG_SVD_SW_RST (SVD_REG_BASE + 0x0A * 2)
/utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/
H A DregPWS.h125 #define SVD_REG_BASE (0x1B00UL) // 0x1B00 - 0x1BFF macro
126 #define REG_SVD_SW_RST (SVD_REG_BASE + 0x0A * 2)
/utopia/UTPA2-700.0.x/modules/pws/hal/maserati/pws/
H A DregPWS.h140 #define SVD_REG_BASE (0x1B00UL) // 0x1B00 - 0x1BFF macro
141 #define REG_SVD_SW_RST ( SVD_REG_BASE + 0X0A*2 )
/utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/
H A DregPWS.h125 #define SVD_REG_BASE (0x1B00UL) // 0x1B00 - 0x1BFF macro
126 #define REG_SVD_SW_RST (SVD_REG_BASE + 0x0A * 2)
/utopia/UTPA2-700.0.x/modules/pws/hal/mainz/pws/
H A DregPWS.h125 #define SVD_REG_BASE (0x1B00UL) // 0x1B00 - 0x1BFF macro
126 #define REG_SVD_SW_RST (SVD_REG_BASE + 0x0A * 2)
/utopia/UTPA2-700.0.x/modules/pws/hal/M7821/pws/
H A DregPWS.h140 #define SVD_REG_BASE (0x1B00UL) // 0x1B00 - 0x1BFF macro
141 #define REG_SVD_SW_RST ( SVD_REG_BASE + 0X0A*2 )
/utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/
H A DregPWS.h140 #define SVD_REG_BASE (0x1B00UL) // 0x1B00 - 0x1BFF macro
141 #define REG_SVD_SW_RST ( SVD_REG_BASE + 0X0A*2 )
/utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/
H A DregPWS.h125 #define SVD_REG_BASE (0x1B00) // 0x1B00 - 0x1BFF macro
126 #define REG_SVD_SW_RST (SVD_REG_BASE + 0x0A * 2)
/utopia/UTPA2-700.0.x/modules/pws/hal/kano/pws/
H A DregPWS.h140 #define SVD_REG_BASE (0x1B00) // 0x1B00 - 0x1BFF macro
141 #define REG_SVD_SW_RST ( SVD_REG_BASE + 0X0A*2 )
/utopia/UTPA2-700.0.x/modules/pws/hal/curry/pws/
H A DregPWS.h140 #define SVD_REG_BASE (0x1B00) // 0x1B00 - 0x1BFF macro
141 #define REG_SVD_SW_RST ( SVD_REG_BASE + 0X0A*2 )

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