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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regJPD.h 98 /// @brief JPD Register Table 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_JPD_H_ 103 #define _REG_JPD_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 /******* Internal table SRAM address *******/ 115 #if (JPD_SUPPORT_3_HUFFMAN_TABLE==true) 116 #define JPD_MEM_SCWGIF_BASE 0x0000 117 #define JPD_MEM_SYMIDX_BASE 0x0400 118 #define JPD_MEM_QTBL_BASE 0x0800 119 #else 120 #define JPD_MEM_SCWGIF_BASE 0x0000 121 #define JPD_MEM_SYMIDX_BASE 0x0200 122 #define JPD_MEM_QTBL_BASE 0x0400 123 #endif 124 /**************************************/ 125 126 //M-Config 127 #define JPD_MWC_WPEN JPD_BIT(0) // bit0 of 2nd byte of BK_JPD_MCONFIG 128 #define JPD_MIF_RST JPD_BIT(3) 129 #define JPD_MIU_SEL (JPD_BIT(1) | JPD_BIT(2)) //bit1 and bit2 of 2nd byte of BK_JPD_MCONFIG 130 #if (JPD_SUPPORT_AUTO_PROTECT==true) 131 #define JPD_AUTO_PROTECT JPD_BIT(0) 132 #endif 133 134 #define JPD_REG_BASE 0x1700 135 136 #define BK_JPD_SCONFIG (JPD_REG_BASE+JPD_OFFSET(0x00)) 137 #define BK_JPD_MCONFIG (JPD_REG_BASE+JPD_OFFSET(0x01)) 138 #define BK_JPD_RSTINTV (JPD_REG_BASE+JPD_OFFSET(0x02)) 139 #define BK_JPD_PIC_H (JPD_REG_BASE+JPD_OFFSET(0x03)) 140 #define BK_JPD_PIC_V (JPD_REG_BASE+JPD_OFFSET(0x04)) 141 #define BK_JPD_ROI_H (JPD_REG_BASE+JPD_OFFSET(0x05)) 142 #define BK_JPD_ROI_V (JPD_REG_BASE+JPD_OFFSET(0x06)) 143 #define BK_JPD_ROI_WIDTH (JPD_REG_BASE+JPD_OFFSET(0x07)) 144 #define BK_JPD_ROI_HEIGHT (JPD_REG_BASE+JPD_OFFSET(0x08)) 145 #define BK_JPD_INTEN (JPD_REG_BASE+JPD_OFFSET(0x09)) 146 #define BK_JPD_EVENTFLAG (JPD_REG_BASE+JPD_OFFSET(0x0A)) 147 #define BK_JPD_RCSMADR_L (JPD_REG_BASE+JPD_OFFSET(0x0B)) 148 #define BK_JPD_RCSMADR_H (JPD_REG_BASE+JPD_OFFSET(0x0C)) 149 #define BK_JPD_RBUF_FLOOR_L (JPD_REG_BASE+JPD_OFFSET(0x0D)) 150 #define BK_JPD_RBUF_FLOOR_H (JPD_REG_BASE+JPD_OFFSET(0x0E)) 151 #define BK_JPD_RBUF_CEIL_L (JPD_REG_BASE+JPD_OFFSET(0x0F)) 152 #define BK_JPD_RBUF_CEIL_H (JPD_REG_BASE+JPD_OFFSET(0x10)) 153 #define BK_JPD_MWBF_SADR_L (JPD_REG_BASE+JPD_OFFSET(0x11)) 154 #define BK_JPD_MWBF_SADR_H (JPD_REG_BASE+JPD_OFFSET(0x12)) 155 #define BK_JPD_MWBF_LINE_NUM (JPD_REG_BASE+JPD_OFFSET(0x13)) 156 #define BK_JPD_CUR_MADR_L (JPD_REG_BASE+JPD_OFFSET(0x14)) 157 #define BK_JPD_CUR_MADR_H (JPD_REG_BASE+JPD_OFFSET(0x15)) 158 #define BK_JPD_CUR_ROWP (JPD_REG_BASE+JPD_OFFSET(0x16)) 159 #define BK_JPD_CUR_CLNP (JPD_REG_BASE+JPD_OFFSET(0x17)) 160 #define BK_JPD_CUR_VIDX (JPD_REG_BASE+JPD_OFFSET(0x18)) 161 #define BK_JPD_BIST_FAIL (JPD_REG_BASE+JPD_OFFSET(0x19)) 162 #define BK_JPD_DBG_MATCHV (JPD_REG_BASE+JPD_OFFSET(0x1A)) 163 #define BK_JPD_DBG_CTRL (JPD_REG_BASE+JPD_OFFSET(0x1B)) 164 #define BK_JPD_SPARE (JPD_REG_BASE+JPD_OFFSET(0x1C)) 165 166 #if (JPD_SUPPORT_AUTO_PROTECT==true) 167 #define BK_JPD_AUTO_PROTECT (JPD_REG_BASE+JPD_OFFSET(0x1F)) 168 #define BK_JPD_MWC_WPEN_L (JPD_REG_BASE+JPD_OFFSET(0x20)) 169 #define BK_JPD_MWC_WPEN_H (JPD_REG_BASE+JPD_OFFSET(0x21)) 170 #endif 171 172 #define BK_JPD_IP_VERSION (JPD_REG_BASE+JPD_OFFSET(0x28)) 173 174 #define BK_JPD_TID_ADR (JPD_REG_BASE+JPD_OFFSET(0x40)) 175 #define BK_JPD_TID_DAT (JPD_REG_BASE+JPD_OFFSET(0x41)) 176 177 // Chip Top 178 #define JPD_CHIPTOP_REG_BASE 0x0B00 179 //#define JPD_CLOCK_S4 (JPD_CHIPTOP_REG_BASE+JPD_OFFSET(0x2D)) // Eris 180 //#define JPD_CLOCK_S4L (JPD_CHIPTOP_REG_BASE+JPD_OFFSET(0x4D)) // Titania 181 //#define JPD_CLOCK (JPD_CHIPTOP_REG_BASE+JPD_OFFSET(0x4D)) // Titania 1/2 182 #define JPD_CLOCK (JPD_CHIPTOP_REG_BASE+JPD_OFFSET(0x35)) // T3/T4/T7/JANUS/U4: (0x580 + 0x35)*2 183 //#define JPD_CLOCK (JPD_CHIPTOP_REG_BASE+JPD_OFFSET(0x16)) // U3: 184 185 // MIU 186 #define JPD_MIU0_BASE 0x1200 187 #define JPD_MIU1_BASE 0x0600 188 #define JPD_MIU0_RQ2_MASK (JPD_MIU0_BASE+JPD_OFFSET(0x43)) //group2 189 #define JPD_MIU1_RQ2_MASK (JPD_MIU1_BASE+JPD_OFFSET(0x43)) //group2 190 #define JPD_MIU0_MIU_SEL2 (JPD_MIU0_BASE+JPD_OFFSET(0x7a)) //group2 191 #define JPD_MIU1_MIU_SEL2 (JPD_MIU1_BASE+JPD_OFFSET(0x7a)) //group2 192 #define JPD_MIU0_CLIENT_JPD JPD_BIT(4) //group3, bit4 of the second byte 193 #define JPD_MIU1_CLIENT_JPD JPD_BIT(4) //group3, bit4 of the second byte 194 195 196 // CHIPTOP 197 #define JPD_CHIPTOP_BASE 0x1E00 198 #define JPD_MIU_GROUP2_I64 (JPD_CHIPTOP_BASE + JPD_OFFSET(0x22)) 199 #define JPD_MIU0_CLIENT_JPD_CS2 JPD_BIT(4) // bit 4 of the second byte 200 #define JPD_MIU0_CLIENT_JPD_CS3 JPD_BIT(2) // bit 2 of the second byte 201 202 203 // NJPD 204 #define NJPD1_REG_BASE 0x23200 205 #define NJPD2_REG_BASE 0x23300 206 #define BK_NJPD1_SPARE00 (NJPD1_REG_BASE+JPD_OFFSET(0x48)) 207 #define BK_NJPD2_SPARE00 (NJPD2_REG_BASE+JPD_OFFSET(0x48)) 208 #define BK_NJPD1_TOP_MARB_PORT_ENABLE (NJPD1_REG_BASE+JPD_OFFSET(0x76)) 209 #define BK_NJPD2_TOP_MARB_PORT_ENABLE (NJPD2_REG_BASE+JPD_OFFSET(0x76)) 210 #define NJPD_TOP_MARB_P0_ENABLE JPD_BIT(0) 211 #define NJPD_TOP_MARB_P1_ENABLE JPD_BIT(1) 212 #define NJPD_TOP_MARB_P2_ENABLE JPD_BIT(2) 213 #define NJPD_TOP_MARB_P0_W_BYPASS_ENABLE JPD_BIT(4) 214 #define NJPD_TOP_MARB_P1_W_BYPASS_ENABLE JPD_BIT(5) 215 #define NJPD_TOP_MARB_P2_W_BYPASS_ENABLE JPD_BIT(6) 216 #define NJPD_TOP_MARB_P0_R_BYPASS_ENABLE JPD_BIT(7) 217 #define NJPD_TOP_MARB_P1_R_BYPASS_ENABLE JPD_BIT(0) // second byte 218 #define NJPD_TOP_MARB_P2_R_BYPASS_ENABLE JPD_BIT(1) // second byte 219 220 /*================================ MJPEG =====================================*/ 221 222 #if 0 223 // from regSVD.h 224 // SVD register 225 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF 226 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08)) 227 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A)) 228 #define REG_SVD_RESET_SWRST JPD_BIT(0) 229 #define REG_SVD_RESET_CPURST JPD_BIT(1) 230 #define REG_SVD_RESET_SWRST_FIN JPD_BIT(2) 231 #define REG_SVD_RESET_CPURST_FIN JPD_BIT(3) 232 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15)) 233 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F)) 234 235 // SVD Chiptop clock 236 #define REG_CKG_SVD 0x1E58 237 #define CKG_SVD_GATED JPD_BIT(0) 238 #define CKG_SVD_INVERT JPD_BIT(1) 239 #define CKG_SVD_MASK JPD_BITMASK(6:2) 240 #define CKG_SVD_240MHZ (0 << 2) 241 #define CKG_SVD_216MHZ (1 << 2) 242 #define CKG_SVD_CLK_MVD_P (2 << 2) 243 #define CKG_SVD_CLK_RVD_P (3 << 2) 244 #define CKG_SVD_CLK_MIU (8 << 2) 245 #define CKG_SVD_XTAL (18 << 2) 246 247 //#define REG_SVD_INT (SVD_REG_BASE + JPD_OFFSET(0x16)) 248 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17)) 249 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18)) 250 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19)) 251 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A)) 252 253 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B)) 254 #define REG_SVD_HI_MBOX0_SET JPD_BIT(0) 255 #define REG_SVD_HI_MBOX1_SET JPD_BIT(1) 256 #define REG_SVD_RISC_MBOX_CLR (SVD_REG_BASE + JPD_OFFSET(0x1C)) 257 #define REG_SVD_RISC_MBOX0_CLR JPD_BIT(0) 258 #define REG_SVD_RISC_MBOX1_CLR JPD_BIT(1) 259 #define REG_SVD_RISC_MBOX_RDY (SVD_REG_BASE + JPD_OFFSET(0x1D)) 260 #define REG_SVD_RISC_MBOX0_RDY JPD_BIT(0) 261 #define REG_SVD_RISC_MBOX1_RDY JPD_BIT(1) 262 #define REG_SVD_HI_MBOX_RDY (SVD_REG_BASE + JPD_OFFSET(0x1E)) 263 #define REG_SVD_HI_MBOX0_RDY JPD_BIT(0) 264 #define REG_SVD_HI_MBOX1_RDY JPD_BIT(1) 265 266 #define REG_SVD_RISC_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x23)) 267 #define REG_SVD_RISC_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x24)) 268 #define REG_SVD_RISC_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x25)) 269 #define REG_SVD_RISC_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x26)) 270 #endif 271 272 273 // TSP 274 #define TSP_REG_BASE 0x1500 275 #define REG_TSP_CTRL (TSP_REG_BASE + JPD_OFFSET(0x7A)) 276 #define REG_TSP_CPU_ENABLE JPD_BIT(0) 277 #define REG_TSP_SW_RSTZ JPD_BIT(1) 278 #define REG_TSP_STC_L (TSP_REG_BASE + JPD_OFFSET(0x30)) 279 #define REG_TSP_STC_H (TSP_REG_BASE + JPD_OFFSET(0x31)) 280 281 282 //------------------------------------------------------------------------------------------------- 283 // Type and Structure 284 //------------------------------------------------------------------------------------------------- 285 286 287 #endif // _REG_JPD_H_ 288 289