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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regJPD.h 98 /// @brief JPD Register Table 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_JPD_H_ 103 #define _REG_JPD_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 /******* Internal table SRAM address *******/ 115 #define JPD_MEM_SCWGIF_BASE 0x0000 116 #define JPD_MEM_SYMIDX_BASE 0x0200 117 #define JPD_MEM_QTBL_BASE 0x0400 118 /**************************************/ 119 120 //M-Config 121 #define JPD_MWC_WPEN JPD_BIT(0) // bit0 of 2nd byte of BK_JPD_MCONFIG 122 #define JPD_MIF_RST JPD_BIT(3) 123 #define JPD_MIU_SEL (JPD_BIT(1) | JPD_BIT(2)) //bit1 and bit2 of 2nd byte of BK_JPD_MCONFIG 124 125 #define JPD_REG_BASE 0x1700 126 127 #define BK_JPD_SCONFIG (JPD_REG_BASE+JPD_OFFSET(0x00)) 128 #define BK_JPD_MCONFIG (JPD_REG_BASE+JPD_OFFSET(0x01)) 129 #define BK_JPD_RSTINTV (JPD_REG_BASE+JPD_OFFSET(0x02)) 130 #define BK_JPD_PIC_H (JPD_REG_BASE+JPD_OFFSET(0x03)) 131 #define BK_JPD_PIC_V (JPD_REG_BASE+JPD_OFFSET(0x04)) 132 #define BK_JPD_ROI_H (JPD_REG_BASE+JPD_OFFSET(0x05)) 133 #define BK_JPD_ROI_V (JPD_REG_BASE+JPD_OFFSET(0x06)) 134 #define BK_JPD_ROI_WIDTH (JPD_REG_BASE+JPD_OFFSET(0x07)) 135 #define BK_JPD_ROI_HEIGHT (JPD_REG_BASE+JPD_OFFSET(0x08)) 136 #define BK_JPD_INTEN (JPD_REG_BASE+JPD_OFFSET(0x09)) 137 #define BK_JPD_EVENTFLAG (JPD_REG_BASE+JPD_OFFSET(0x0A)) 138 #define BK_JPD_RCSMADR_L (JPD_REG_BASE+JPD_OFFSET(0x0B)) 139 #define BK_JPD_RCSMADR_H (JPD_REG_BASE+JPD_OFFSET(0x0C)) 140 #define BK_JPD_RBUF_FLOOR_L (JPD_REG_BASE+JPD_OFFSET(0x0D)) 141 #define BK_JPD_RBUF_FLOOR_H (JPD_REG_BASE+JPD_OFFSET(0x0E)) 142 #define BK_JPD_RBUF_CEIL_L (JPD_REG_BASE+JPD_OFFSET(0x0F)) 143 #define BK_JPD_RBUF_CEIL_H (JPD_REG_BASE+JPD_OFFSET(0x10)) 144 #define BK_JPD_MWBF_SADR_L (JPD_REG_BASE+JPD_OFFSET(0x11)) 145 #define BK_JPD_MWBF_SADR_H (JPD_REG_BASE+JPD_OFFSET(0x12)) 146 #define BK_JPD_MWBF_LINE_NUM (JPD_REG_BASE+JPD_OFFSET(0x13)) 147 #define BK_JPD_CUR_MADR_L (JPD_REG_BASE+JPD_OFFSET(0x14)) 148 #define BK_JPD_CUR_MADR_H (JPD_REG_BASE+JPD_OFFSET(0x15)) 149 #define BK_JPD_CUR_ROWP (JPD_REG_BASE+JPD_OFFSET(0x16)) 150 #define BK_JPD_CUR_CLNP (JPD_REG_BASE+JPD_OFFSET(0x17)) 151 #define BK_JPD_CUR_VIDX (JPD_REG_BASE+JPD_OFFSET(0x18)) 152 #define BK_JPD_BIST_FAIL (JPD_REG_BASE+JPD_OFFSET(0x19)) 153 #define BK_JPD_DBG_MATCHV (JPD_REG_BASE+JPD_OFFSET(0x1A)) 154 #define BK_JPD_DBG_CTRL (JPD_REG_BASE+JPD_OFFSET(0x1B)) 155 #define BK_JPD_SPARE (JPD_REG_BASE+JPD_OFFSET(0x1C)) 156 157 #define BK_JPD_IP_VERSION (JPD_REG_BASE+JPD_OFFSET(0x28)) 158 159 #define BK_JPD_TID_ADR (JPD_REG_BASE+JPD_OFFSET(0x40)) 160 #define BK_JPD_TID_DAT (JPD_REG_BASE+JPD_OFFSET(0x41)) 161 162 // Chip Top 163 #define JPD_CHIPTOP_REG_BASE 0x0B00 164 //#define JPD_CLOCK_S4 (JPD_CHIPTOP_REG_BASE+JPD_OFFSET(0x2D)) // Eris 165 //#define JPD_CLOCK_S4L (JPD_CHIPTOP_REG_BASE+JPD_OFFSET(0x4D)) // Titania 166 //#define JPD_CLOCK (JPD_CHIPTOP_REG_BASE+JPD_OFFSET(0x4D)) // Titania 1/2 167 #define JPD_CLOCK (JPD_CHIPTOP_REG_BASE+JPD_OFFSET(0x35)) // T3/T4/T7/JANUS/U4: (0x580 + 0x35)*2 168 //#define JPD_CLOCK (JPD_CHIPTOP_REG_BASE+JPD_OFFSET(0x16)) // U3: 169 170 // MIU 171 #define JPD_MIU0_BASE 0x1200 172 #define JPD_MIU1_BASE 0x0600 173 #define JPD_MIU0_RQ2_MASK (JPD_MIU0_BASE+JPD_OFFSET(0x43)) //group2 174 #define JPD_MIU1_RQ2_MASK (JPD_MIU1_BASE+JPD_OFFSET(0x43)) //group2 175 #define JPD_MIU0_MIU_SEL2 (JPD_MIU0_BASE+JPD_OFFSET(0x7a)) //group2 176 #define JPD_MIU1_MIU_SEL2 (JPD_MIU1_BASE+JPD_OFFSET(0x7a)) //group2 177 #define JPD_MIU0_CLIENT_JPD JPD_BIT(4) //group3, bit4 of the second byte 178 #define JPD_MIU1_CLIENT_JPD JPD_BIT(4) //group3, bit4 of the second byte 179 180 /*================================ MJPEG =====================================*/ 181 182 #if 0 183 // from regSVD.h 184 // SVD register 185 #define SVD_REG_BASE 0x1B00 // 0x1B00 - 0x1BFF 186 #define REG_SVD_CPU_SDR_BASE_L (SVD_REG_BASE + JPD_OFFSET(0x08)) 187 #define REG_SVD_RESET (SVD_REG_BASE + JPD_OFFSET(0x0A)) 188 #define REG_SVD_RESET_SWRST JPD_BIT(0) 189 #define REG_SVD_RESET_CPURST JPD_BIT(1) 190 #define REG_SVD_RESET_SWRST_FIN JPD_BIT(2) 191 #define REG_SVD_RESET_CPURST_FIN JPD_BIT(3) 192 #define REG_SVD_LDEND_EN (SVD_REG_BASE + JPD_OFFSET(0x15)) 193 #define REG_SVD_MIU_OFFSET_H0 (SVD_REG_BASE + JPD_OFFSET(0x1F)) 194 195 // SVD Chiptop clock 196 #define REG_CKG_SVD 0x1E58 197 #define CKG_SVD_GATED JPD_BIT(0) 198 #define CKG_SVD_INVERT JPD_BIT(1) 199 #define CKG_SVD_MASK JPD_BITMASK(6:2) 200 #define CKG_SVD_240MHZ (0 << 2) 201 #define CKG_SVD_216MHZ (1 << 2) 202 #define CKG_SVD_CLK_MVD_P (2 << 2) 203 #define CKG_SVD_CLK_RVD_P (3 << 2) 204 #define CKG_SVD_CLK_MIU (8 << 2) 205 #define CKG_SVD_XTAL (18 << 2) 206 207 //#define REG_SVD_INT (SVD_REG_BASE + JPD_OFFSET(0x16)) 208 #define REG_SVD_HI_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x17)) 209 #define REG_SVD_HI_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x18)) 210 #define REG_SVD_HI_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x19)) 211 #define REG_SVD_HI_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x1A)) 212 213 #define REG_SVD_HI_MBOX_SET (SVD_REG_BASE + JPD_OFFSET(0x1B)) 214 #define REG_SVD_HI_MBOX0_SET JPD_BIT(0) 215 #define REG_SVD_HI_MBOX1_SET JPD_BIT(1) 216 #define REG_SVD_RISC_MBOX_CLR (SVD_REG_BASE + JPD_OFFSET(0x1C)) 217 #define REG_SVD_RISC_MBOX0_CLR JPD_BIT(0) 218 #define REG_SVD_RISC_MBOX1_CLR JPD_BIT(1) 219 #define REG_SVD_RISC_MBOX_RDY (SVD_REG_BASE + JPD_OFFSET(0x1D)) 220 #define REG_SVD_RISC_MBOX0_RDY JPD_BIT(0) 221 #define REG_SVD_RISC_MBOX1_RDY JPD_BIT(1) 222 #define REG_SVD_HI_MBOX_RDY (SVD_REG_BASE + JPD_OFFSET(0x1E)) 223 #define REG_SVD_HI_MBOX0_RDY JPD_BIT(0) 224 #define REG_SVD_HI_MBOX1_RDY JPD_BIT(1) 225 226 #define REG_SVD_RISC_MBOX0_L (SVD_REG_BASE + JPD_OFFSET(0x23)) 227 #define REG_SVD_RISC_MBOX0_H (SVD_REG_BASE + JPD_OFFSET(0x24)) 228 #define REG_SVD_RISC_MBOX1_L (SVD_REG_BASE + JPD_OFFSET(0x25)) 229 #define REG_SVD_RISC_MBOX1_H (SVD_REG_BASE + JPD_OFFSET(0x26)) 230 #endif 231 232 233 // TSP 234 #define TSP_REG_BASE 0x1500 235 #define REG_TSP_CTRL (TSP_REG_BASE + JPD_OFFSET(0x7A)) 236 #define REG_TSP_CPU_ENABLE JPD_BIT(0) 237 #define REG_TSP_SW_RSTZ JPD_BIT(1) 238 #define REG_TSP_STC_L (TSP_REG_BASE + JPD_OFFSET(0x30)) 239 #define REG_TSP_STC_H (TSP_REG_BASE + JPD_OFFSET(0x31)) 240 241 242 //------------------------------------------------------------------------------------------------- 243 // Type and Structure 244 //------------------------------------------------------------------------------------------------- 245 246 247 #endif // _REG_JPD_H_ 248 249