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Searched refs:REG_TOP_HVD_CLK (Results 1 – 25 of 28) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/hvd/
H A DhalHVD.c1578 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_PowerCtrl()
1579 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1580 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1581 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_PowerCtrl()
1586 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_PowerCtrl()
1587 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1588 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1589 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_PowerCtrl()
H A DregHVD.h399 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/hvd/
H A DhalHVD.c1578 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_PowerCtrl()
1579 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1580 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1581 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_PowerCtrl()
1586 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_PowerCtrl()
1587 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1588 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1589 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_PowerCtrl()
H A DregHVD.h399 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/hvd/
H A DhalHVD.c1578 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_PowerCtrl()
1579 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1580 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1581 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_PowerCtrl()
1586 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_PowerCtrl()
1587 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1588 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1589 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_PowerCtrl()
H A DregHVD.h399 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/hvd/
H A DhalHVD.c1578 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_PowerCtrl()
1579 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1580 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1581 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_PowerCtrl()
1586 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_PowerCtrl()
1587 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1588 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1589 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_PowerCtrl()
H A DregHVD.h399 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/hvd/
H A DhalHVD.c1578 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_PowerCtrl()
1579 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1580 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1581 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_PowerCtrl()
1586 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_PowerCtrl()
1587 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1588 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1589 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_PowerCtrl()
H A DregHVD.h399 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/hvd/
H A DhalHVD.c1578 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_PowerCtrl()
1579 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1580 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1581 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_PowerCtrl()
1586 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_PowerCtrl()
1587 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1588 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_PowerCtrl()
1589 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_PowerCtrl()
H A DregHVD.h399 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/hvd_ex/
H A DhalHVD_EX.c2556 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2557 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2558 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2559 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2566 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2567 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2568 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2569 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/hvd_ex/
H A DhalHVD_EX.c2556 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2557 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2558 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2559 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2566 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2567 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2568 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2569 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h495 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/hvd_ex/
H A DhalHVD_EX.c2556 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2557 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2558 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2559 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2566 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2567 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2568 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2569 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/hvd_ex/
H A DhalHVD_EX.c2556 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2557 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2558 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2559 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2566 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2567 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2568 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2569 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h495 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/hvd_ex/
H A DhalHVD_EX.c2556 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2557 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2558 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2559 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2566 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2567 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2568 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2569 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h495 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/hvd_ex/
H A DhalHVD_EX.c2556 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2557 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2558 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2559 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2566 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2567 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2568 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2569 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/hvd_ex/
H A DhalHVD_EX.c2556 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2557 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2558 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2559 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2566 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2567 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2568 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2569 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h495 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/hvd_ex/
H A DhalHVD_EX.c2556 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2557 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2558 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2559 _HVD_WriteWordMask(REG_TOP_HVD_CLK, ~TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
2566 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_HVD_VP8_DIS, TOP_CLK_HVD_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
2567 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_MASK, TOP_CLK_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2568 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_RM_MIU_HVD_MASK, TOP_CLK_RM_MIU_HVD_MASK); in HAL_HVD_EX_PowerCtrl()
2569 _HVD_WriteWordMask(REG_TOP_HVD_CLK, TOP_CLK_MIU_HVD_VP8_MASK, TOP_CLK_MIU_HVD_VP8_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h495 #define REG_TOP_HVD_CLK (CLKGEN0_REG_BASE+(0x003F<<1)) macro

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