Home
last modified time | relevance | path

Searched refs:REG_TC_VE_ENC2_00_H (Results 1 – 12 of 12) sorted by relevance

/utopia/UTPA2-700.0.x/modules/ve/hal/kano/ve/
H A Dmdrv_macrovision_tbl.c140 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
180 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
220 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
260 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x1E/*ALL*/, },
300 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x06/*ALL*/, },
340 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
380 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x1E/*ALL*/, },
420 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
460 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
500 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x18/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/curry/ve/
H A Dmdrv_macrovision_tbl.c140 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
180 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
220 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
260 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x1E/*ALL*/, },
300 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x06/*ALL*/, },
340 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
380 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x1E/*ALL*/, },
420 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
460 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
500 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x18/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/k6/ve/
H A Dmdrv_macrovision_tbl.c140 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
180 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
220 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
260 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x1E/*ALL*/, },
300 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x06/*ALL*/, },
340 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
380 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x1E/*ALL*/, },
420 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
460 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
500 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x18/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/k6lite/ve/
H A Dmdrv_macrovision_tbl.c140 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
180 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
220 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
260 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x1E/*ALL*/, },
300 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x06/*ALL*/, },
340 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
380 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x1E/*ALL*/, },
420 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
460 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
500 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x18/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/ve/hal/k6lite/ve/include/
H A Dmdrv_macrovision_tbl.h743 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01) macro
H A Dmdrv_dcs_tbl.h844 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01) macro
/utopia/UTPA2-700.0.x/modules/ve/hal/curry/ve/include/
H A Dmdrv_macrovision_tbl.h743 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01) macro
H A Dmdrv_dcs_tbl.h844 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01) macro
/utopia/UTPA2-700.0.x/modules/ve/hal/kano/ve/include/
H A Dmdrv_macrovision_tbl.h743 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01) macro
H A Dmdrv_dcs_tbl.h844 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01) macro
/utopia/UTPA2-700.0.x/modules/ve/hal/k6/ve/include/
H A Dmdrv_macrovision_tbl.h743 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01) macro
H A Dmdrv_dcs_tbl.h844 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01) macro