xref: /utopia/UTPA2-700.0.x/modules/ve/hal/k6/ve/mdrv_macrovision_tbl.c (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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//******************************************************************************
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//****************************************************
// MACROVISION Drive Chip           : Uranus4_Macrovision_Driver
// MACROVISION Excel CodeGen Version: 1.04
// MACROVISION Excel SW      Version: 1.1
// MACROVISION Excel update date    : 2013/9/17 11:39
//****************************************************

#ifndef _DRVMACROVISION_TBL_C_
#define _DRVMACROVISION_TBL_C_

#include "MsCommon.h"
#include "mdrv_macrovision_tbl.h"

//****************************************************
// MACROVISION  MACROVISION_NTSC_TYPE1
//****************************************************
MS_U8 MST_MACROVISION_MACROVISION_NTSC_TYPE1_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TYPE1_MACROVISION_NUMS]=
{                 // Reg           Mask  Value
 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x36/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x04/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x25/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x04/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x38/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1B/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x1B/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xF8/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x0F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x0F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x85/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xD4/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x28/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0xF8/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x1F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TABLE_END)   , 0x00, 0x00,  }
};

//****************************************************
// MACROVISION  MACROVISION_NTSC_TYPE2
//****************************************************
MS_U8 MST_MACROVISION_MACROVISION_NTSC_TYPE2_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TYPE2_MACROVISION_NUMS]=
{                 // Reg           Mask  Value
 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x04/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x25/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x04/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x38/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1B/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x1B/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xF8/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x0F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x0F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x85/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xD4/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x28/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0xF8/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x1F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TABLE_END)   , 0x00, 0x00,  }
};

//****************************************************
// MACROVISION  MACROVISION_NTSC_TYPE3
//****************************************************
MS_U8 MST_MACROVISION_MACROVISION_NTSC_TYPE3_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TYPE3_MACROVISION_NUMS]=
{                 // Reg           Mask  Value
 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x17/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x21/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x28/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1B/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x1B/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xF8/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x0F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x0F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x85/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xD4/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x28/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0xF8/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x1F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TABLE_END)   , 0x00, 0x00,  }
};

//****************************************************
// MACROVISION  MACROVISION_NTSC_TEST_N01
//****************************************************
MS_U8 MST_MACROVISION_MACROVISION_NTSC_TEST_N01_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TEST_N01_MACROVISION_NUMS]=
{                 // Reg           Mask  Value
 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x17/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x21/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x28/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0xC0/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x19/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x1C/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0xC0/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xF8/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x0F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x07/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x7E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x0F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x0E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x91/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x85/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xEC/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x14/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x1E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x02/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x78/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x18/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x02/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TABLE_END)   , 0x00, 0x00,  }
};

//****************************************************
// MACROVISION  MACROVISION_NTSC_TEST_N02
//****************************************************
MS_U8 MST_MACROVISION_MACROVISION_NTSC_TEST_N02_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TEST_N02_MACROVISION_NUMS]=
{                 // Reg           Mask  Value
 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x2F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x0A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x1A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x0D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x02/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x20/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0xC0/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x24/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x25/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x07/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xB8/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x36/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0xCF/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x6D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x23/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x13/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x70/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x94/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xF7/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x06/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x78/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x02/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TABLE_END)   , 0x00, 0x00,  }
};

//****************************************************
// MACROVISION  MACROVISION_NTSC_TYPE2_TTX
//****************************************************
MS_U8 MST_MACROVISION_MACROVISION_NTSC_TYPE2_TTX_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TYPE2_TTX_MACROVISION_NUMS]=
{                 // Reg           Mask  Value
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x04/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x25/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x04/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x38/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1B/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x1B/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x04/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x0F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x0F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x85/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xD4/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x28/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0xF8/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x1F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TABLE_END)   , 0x00, 0x00,  }
};

//****************************************************
// MACROVISION  MACROVISION_NTSC_TEST_N01_TTX
//****************************************************
MS_U8 MST_MACROVISION_MACROVISION_NTSC_TEST_N01_TTX_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TEST_N01_TTX_MACROVISION_NUMS]=
{                 // Reg           Mask  Value
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x17/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x21/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x40/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x28/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0xC0/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x19/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x1C/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0xC0/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x0C/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x07/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x7E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x0F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x0E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x91/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x85/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xEC/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x14/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x1E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x02/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x78/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x18/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x02/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TABLE_END)   , 0x00, 0x00,  }
};

//****************************************************
// MACROVISION  MACROVISION_PAL_TYPE1_2_3
//****************************************************
MS_U8 MST_MACROVISION_MACROVISION_PAL_TYPE1_2_3_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_PAL_TYPE1_2_3_MACROVISION_NUMS]=
{                 // Reg           Mask  Value
 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x36/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x2A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x10/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1C/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x3D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xFE/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x54/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0xFE/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x7E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x9D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xDC/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x20/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x07/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x50/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x15/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TABLE_END)   , 0x00, 0x00,  }
};

//****************************************************
// MACROVISION  MACROVISION_PAL_TEST_P01
//****************************************************
MS_U8 MST_MACROVISION_MACROVISION_PAL_TEST_P01_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_PAL_TEST_P01_MACROVISION_NUMS]=
{                 // Reg           Mask  Value
 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x2A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x10/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xE0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1C/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x3D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xFE/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x54/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0xFE/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x7E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x9D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xDC/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x20/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x07/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x50/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x15/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x02/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TABLE_END)   , 0x00, 0x00,  }
};

//****************************************************
// MACROVISION  MACROVISION_PAL_TEST_P02
//****************************************************
MS_U8 MST_MACROVISION_MACROVISION_PAL_TEST_P02_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_PAL_TEST_P02_MACROVISION_NUMS]=
{                 // Reg           Mask  Value
 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x2A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x10/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0xC0/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x23/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x12/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0xC0/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x0A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xC6/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x78/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x43/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x1F/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x53/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0xA3/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0xF0/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x8E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xF1/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x1C/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x18/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x02/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x38/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x14/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x02/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TABLE_END)   , 0x00, 0x00,  }
};

//****************************************************
// MACROVISION  MACROVISION_PAL_TYPE1_2_3_TTX
//****************************************************
MS_U8 MST_MACROVISION_MACROVISION_PAL_TYPE1_2_3_TTX_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_PAL_TYPE1_2_3_TTX_MACROVISION_NUMS]=
{                 // Reg           Mask  Value
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x36/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x2A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x10/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1C/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x3D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x54/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0xFE/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x7E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x9D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xDC/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x20/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x07/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x50/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x15/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TABLE_END)   , 0x00, 0x00,  }
};

//****************************************************
// MACROVISION  MACROVISION_PAL_TEST_P01_TTX
//****************************************************
MS_U8 MST_MACROVISION_MACROVISION_PAL_TEST_P01_TTX_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_PAL_TEST_P01_TTX_MACROVISION_NUMS]=
{                 // Reg           Mask  Value
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x2A/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x80/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x08/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x10/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xE0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1C/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x3D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x54/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x01/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0xFE/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x7E/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x9D/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xDC/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x20/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x07/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x50/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x15/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x02/*ALL*/, },
 { DRV_MACROVISION_REG(REG_TABLE_END)   , 0x00, 0x00,  }
};

MACROVISION_TAB_INFO MACROVISIONMAP_Main[MACROVISION_TYPE_NUMS]=
{
{
*MST_MACROVISION_MACROVISION_NTSC_TYPE1_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION,
},
{
*MST_MACROVISION_MACROVISION_NTSC_TYPE2_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION,
},
{
*MST_MACROVISION_MACROVISION_NTSC_TYPE3_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION,
},
{
*MST_MACROVISION_MACROVISION_NTSC_TEST_N01_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION,
},
{
*MST_MACROVISION_MACROVISION_NTSC_TEST_N02_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION,
},
{
*MST_MACROVISION_MACROVISION_NTSC_TYPE2_TTX_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION,
},
{
*MST_MACROVISION_MACROVISION_NTSC_TEST_N01_TTX_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION,
},
{
*MST_MACROVISION_MACROVISION_PAL_TYPE1_2_3_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION,
},
{
*MST_MACROVISION_MACROVISION_PAL_TEST_P01_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION,
},
{
*MST_MACROVISION_MACROVISION_PAL_TEST_P02_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION,
},
{
*MST_MACROVISION_MACROVISION_PAL_TYPE1_2_3_TTX_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION,
},
{
*MST_MACROVISION_MACROVISION_PAL_TEST_P01_TTX_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION,
},
};

#endif