1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //**************************************************** 96 // MACROVISION Drive Chip : Uranus4_Macrovision_Driver 97 // MACROVISION Excel CodeGen Version: 1.04 98 // MACROVISION Excel SW Version: 1.1 99 // MACROVISION Excel update date : 2013/9/17 11:39 100 //**************************************************** 101 102 #ifndef _DRVMACROVISION_TBL_C_ 103 #define _DRVMACROVISION_TBL_C_ 104 105 #include "MsCommon.h" 106 #include "mdrv_macrovision_tbl.h" 107 108 //**************************************************** 109 // MACROVISION MACROVISION_NTSC_TYPE1 110 //**************************************************** 111 MS_U8 MST_MACROVISION_MACROVISION_NTSC_TYPE1_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TYPE1_MACROVISION_NUMS]= 112 { // Reg Mask Value 113 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x36/*ALL*/, }, 114 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x00/*ALL*/, }, 115 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1D/*ALL*/, }, 116 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x40/*ALL*/, }, 117 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x04/*ALL*/, }, 118 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x25/*ALL*/, }, 119 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x40/*ALL*/, }, 120 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x04/*ALL*/, }, 121 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x01/*ALL*/, }, 122 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x38/*ALL*/, }, 123 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0x00/*ALL*/, }, 124 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, }, 125 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1B/*ALL*/, }, 126 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x1B/*ALL*/, }, 127 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, }, 128 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 129 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xF8/*ALL*/, }, 130 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, }, 131 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x00/*ALL*/, }, 132 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x00/*ALL*/, }, 133 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x0F/*ALL*/, }, 134 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x0F/*ALL*/, }, 135 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, }, 136 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x85/*ALL*/, }, 137 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xD4/*ALL*/, }, 138 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x28/*ALL*/, }, 139 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, }, 140 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, }, 141 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x01/*ALL*/, }, 142 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0xF8/*ALL*/, }, 143 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x1F/*ALL*/, }, 144 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x00/*ALL*/, }, 145 { DRV_MACROVISION_REG(REG_TABLE_END) , 0x00, 0x00, } 146 }; 147 148 //**************************************************** 149 // MACROVISION MACROVISION_NTSC_TYPE2 150 //**************************************************** 151 MS_U8 MST_MACROVISION_MACROVISION_NTSC_TYPE2_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TYPE2_MACROVISION_NUMS]= 152 { // Reg Mask Value 153 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, }, 154 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, }, 155 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1D/*ALL*/, }, 156 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x40/*ALL*/, }, 157 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x04/*ALL*/, }, 158 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x25/*ALL*/, }, 159 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x40/*ALL*/, }, 160 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x04/*ALL*/, }, 161 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x01/*ALL*/, }, 162 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x38/*ALL*/, }, 163 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0x00/*ALL*/, }, 164 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, }, 165 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1B/*ALL*/, }, 166 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x1B/*ALL*/, }, 167 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, }, 168 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 169 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xF8/*ALL*/, }, 170 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, }, 171 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x00/*ALL*/, }, 172 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x00/*ALL*/, }, 173 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x0F/*ALL*/, }, 174 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x0F/*ALL*/, }, 175 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, }, 176 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x85/*ALL*/, }, 177 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xD4/*ALL*/, }, 178 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x28/*ALL*/, }, 179 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, }, 180 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, }, 181 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x01/*ALL*/, }, 182 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0xF8/*ALL*/, }, 183 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x1F/*ALL*/, }, 184 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x00/*ALL*/, }, 185 { DRV_MACROVISION_REG(REG_TABLE_END) , 0x00, 0x00, } 186 }; 187 188 //**************************************************** 189 // MACROVISION MACROVISION_NTSC_TYPE3 190 //**************************************************** 191 MS_U8 MST_MACROVISION_MACROVISION_NTSC_TYPE3_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TYPE3_MACROVISION_NUMS]= 192 { // Reg Mask Value 193 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, }, 194 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, }, 195 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x17/*ALL*/, }, 196 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x40/*ALL*/, }, 197 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x05/*ALL*/, }, 198 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x21/*ALL*/, }, 199 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x40/*ALL*/, }, 200 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x05/*ALL*/, }, 201 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, }, 202 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x28/*ALL*/, }, 203 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0x80/*ALL*/, }, 204 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, }, 205 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1B/*ALL*/, }, 206 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x1B/*ALL*/, }, 207 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, }, 208 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 209 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xF8/*ALL*/, }, 210 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x07/*ALL*/, }, 211 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x00/*ALL*/, }, 212 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x00/*ALL*/, }, 213 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x0F/*ALL*/, }, 214 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x0F/*ALL*/, }, 215 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, }, 216 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x85/*ALL*/, }, 217 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xD4/*ALL*/, }, 218 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x28/*ALL*/, }, 219 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, }, 220 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, }, 221 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x01/*ALL*/, }, 222 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0xF8/*ALL*/, }, 223 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x1F/*ALL*/, }, 224 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x00/*ALL*/, }, 225 { DRV_MACROVISION_REG(REG_TABLE_END) , 0x00, 0x00, } 226 }; 227 228 //**************************************************** 229 // MACROVISION MACROVISION_NTSC_TEST_N01 230 //**************************************************** 231 MS_U8 MST_MACROVISION_MACROVISION_NTSC_TEST_N01_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TEST_N01_MACROVISION_NUMS]= 232 { // Reg Mask Value 233 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, }, 234 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, }, 235 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x17/*ALL*/, }, 236 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x40/*ALL*/, }, 237 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x05/*ALL*/, }, 238 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x21/*ALL*/, }, 239 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x40/*ALL*/, }, 240 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x05/*ALL*/, }, 241 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, }, 242 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x28/*ALL*/, }, 243 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0xC0/*ALL*/, }, 244 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, }, 245 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x19/*ALL*/, }, 246 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x1C/*ALL*/, }, 247 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0xC0/*ALL*/, }, 248 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x08/*ALL*/, }, 249 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xF8/*ALL*/, }, 250 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x0F/*ALL*/, }, 251 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x07/*ALL*/, }, 252 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x7E/*ALL*/, }, 253 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x0F/*ALL*/, }, 254 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x0E/*ALL*/, }, 255 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x91/*ALL*/, }, 256 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x85/*ALL*/, }, 257 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xEC/*ALL*/, }, 258 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x14/*ALL*/, }, 259 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, }, 260 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x1E/*ALL*/, }, 261 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x02/*ALL*/, }, 262 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x78/*ALL*/, }, 263 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x18/*ALL*/, }, 264 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x02/*ALL*/, }, 265 { DRV_MACROVISION_REG(REG_TABLE_END) , 0x00, 0x00, } 266 }; 267 268 //**************************************************** 269 // MACROVISION MACROVISION_NTSC_TEST_N02 270 //**************************************************** 271 MS_U8 MST_MACROVISION_MACROVISION_NTSC_TEST_N02_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TEST_N02_MACROVISION_NUMS]= 272 { // Reg Mask Value 273 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, }, 274 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, }, 275 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x2F/*ALL*/, }, 276 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x80/*ALL*/, }, 277 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x0A/*ALL*/, }, 278 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x1A/*ALL*/, }, 279 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x80/*ALL*/, }, 280 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x0D/*ALL*/, }, 281 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x02/*ALL*/, }, 282 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x20/*ALL*/, }, 283 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0xC0/*ALL*/, }, 284 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, }, 285 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x24/*ALL*/, }, 286 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x25/*ALL*/, }, 287 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x40/*ALL*/, }, 288 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x07/*ALL*/, }, 289 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xB8/*ALL*/, }, 290 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x36/*ALL*/, }, 291 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0xCF/*ALL*/, }, 292 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x6D/*ALL*/, }, 293 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x23/*ALL*/, }, 294 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x13/*ALL*/, }, 295 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x70/*ALL*/, }, 296 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x94/*ALL*/, }, 297 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xF7/*ALL*/, }, 298 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x08/*ALL*/, }, 299 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, }, 300 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x06/*ALL*/, }, 301 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x05/*ALL*/, }, 302 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x78/*ALL*/, }, 303 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x00/*ALL*/, }, 304 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x02/*ALL*/, }, 305 { DRV_MACROVISION_REG(REG_TABLE_END) , 0x00, 0x00, } 306 }; 307 308 //**************************************************** 309 // MACROVISION MACROVISION_NTSC_TYPE2_TTX 310 //**************************************************** 311 MS_U8 MST_MACROVISION_MACROVISION_NTSC_TYPE2_TTX_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TYPE2_TTX_MACROVISION_NUMS]= 312 { // Reg Mask Value 313 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, }, 314 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, }, 315 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1D/*ALL*/, }, 316 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x40/*ALL*/, }, 317 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x04/*ALL*/, }, 318 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x25/*ALL*/, }, 319 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x40/*ALL*/, }, 320 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x04/*ALL*/, }, 321 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x01/*ALL*/, }, 322 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x38/*ALL*/, }, 323 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0x00/*ALL*/, }, 324 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, }, 325 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1B/*ALL*/, }, 326 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x1B/*ALL*/, }, 327 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, }, 328 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x09/*ALL*/, }, 329 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0x00/*ALL*/, }, 330 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x04/*ALL*/, }, 331 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x00/*ALL*/, }, 332 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x00/*ALL*/, }, 333 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x0F/*ALL*/, }, 334 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x0F/*ALL*/, }, 335 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, }, 336 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x85/*ALL*/, }, 337 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xD4/*ALL*/, }, 338 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x28/*ALL*/, }, 339 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, }, 340 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, }, 341 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x01/*ALL*/, }, 342 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0xF8/*ALL*/, }, 343 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x1F/*ALL*/, }, 344 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x00/*ALL*/, }, 345 { DRV_MACROVISION_REG(REG_TABLE_END) , 0x00, 0x00, } 346 }; 347 348 //**************************************************** 349 // MACROVISION MACROVISION_NTSC_TEST_N01_TTX 350 //**************************************************** 351 MS_U8 MST_MACROVISION_MACROVISION_NTSC_TEST_N01_TTX_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_NTSC_TEST_N01_TTX_MACROVISION_NUMS]= 352 { // Reg Mask Value 353 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, }, 354 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, }, 355 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x17/*ALL*/, }, 356 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x40/*ALL*/, }, 357 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x05/*ALL*/, }, 358 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x21/*ALL*/, }, 359 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x40/*ALL*/, }, 360 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x05/*ALL*/, }, 361 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, }, 362 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x28/*ALL*/, }, 363 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0xC0/*ALL*/, }, 364 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, }, 365 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x19/*ALL*/, }, 366 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x1C/*ALL*/, }, 367 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0xC0/*ALL*/, }, 368 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x08/*ALL*/, }, 369 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0x00/*ALL*/, }, 370 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x0C/*ALL*/, }, 371 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x07/*ALL*/, }, 372 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x7E/*ALL*/, }, 373 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x0F/*ALL*/, }, 374 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x0E/*ALL*/, }, 375 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x91/*ALL*/, }, 376 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x85/*ALL*/, }, 377 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xEC/*ALL*/, }, 378 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x14/*ALL*/, }, 379 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, }, 380 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x1E/*ALL*/, }, 381 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x02/*ALL*/, }, 382 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x78/*ALL*/, }, 383 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x18/*ALL*/, }, 384 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x02/*ALL*/, }, 385 { DRV_MACROVISION_REG(REG_TABLE_END) , 0x00, 0x00, } 386 }; 387 388 //**************************************************** 389 // MACROVISION MACROVISION_PAL_TYPE1_2_3 390 //**************************************************** 391 MS_U8 MST_MACROVISION_MACROVISION_PAL_TYPE1_2_3_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_PAL_TYPE1_2_3_MACROVISION_NUMS]= 392 { // Reg Mask Value 393 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x36/*ALL*/, }, 394 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x00/*ALL*/, }, 395 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1A/*ALL*/, }, 396 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x80/*ALL*/, }, 397 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x08/*ALL*/, }, 398 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x2A/*ALL*/, }, 399 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x80/*ALL*/, }, 400 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x08/*ALL*/, }, 401 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, }, 402 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x10/*ALL*/, }, 403 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0x00/*ALL*/, }, 404 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, }, 405 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1C/*ALL*/, }, 406 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x3D/*ALL*/, }, 407 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, }, 408 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, }, 409 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xFE/*ALL*/, }, 410 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, }, 411 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x54/*ALL*/, }, 412 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x01/*ALL*/, }, 413 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0xFE/*ALL*/, }, 414 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x7E/*ALL*/, }, 415 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, }, 416 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x9D/*ALL*/, }, 417 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xDC/*ALL*/, }, 418 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x20/*ALL*/, }, 419 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, }, 420 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, }, 421 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x07/*ALL*/, }, 422 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x50/*ALL*/, }, 423 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x15/*ALL*/, }, 424 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x00/*ALL*/, }, 425 { DRV_MACROVISION_REG(REG_TABLE_END) , 0x00, 0x00, } 426 }; 427 428 //**************************************************** 429 // MACROVISION MACROVISION_PAL_TEST_P01 430 //**************************************************** 431 MS_U8 MST_MACROVISION_MACROVISION_PAL_TEST_P01_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_PAL_TEST_P01_MACROVISION_NUMS]= 432 { // Reg Mask Value 433 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, }, 434 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, }, 435 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1A/*ALL*/, }, 436 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x80/*ALL*/, }, 437 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x08/*ALL*/, }, 438 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x2A/*ALL*/, }, 439 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x80/*ALL*/, }, 440 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x08/*ALL*/, }, 441 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, }, 442 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x10/*ALL*/, }, 443 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xE0, 0x00/*ALL*/, }, 444 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, }, 445 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1C/*ALL*/, }, 446 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x3D/*ALL*/, }, 447 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, }, 448 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, }, 449 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xFE/*ALL*/, }, 450 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, }, 451 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x54/*ALL*/, }, 452 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x01/*ALL*/, }, 453 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0xFE/*ALL*/, }, 454 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x7E/*ALL*/, }, 455 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, }, 456 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x9D/*ALL*/, }, 457 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xDC/*ALL*/, }, 458 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x20/*ALL*/, }, 459 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, }, 460 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, }, 461 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x07/*ALL*/, }, 462 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x50/*ALL*/, }, 463 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x15/*ALL*/, }, 464 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x02/*ALL*/, }, 465 { DRV_MACROVISION_REG(REG_TABLE_END) , 0x00, 0x00, } 466 }; 467 468 //**************************************************** 469 // MACROVISION MACROVISION_PAL_TEST_P02 470 //**************************************************** 471 MS_U8 MST_MACROVISION_MACROVISION_PAL_TEST_P02_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_PAL_TEST_P02_MACROVISION_NUMS]= 472 { // Reg Mask Value 473 //{ DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, }, 474 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, }, 475 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1A/*ALL*/, }, 476 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x80/*ALL*/, }, 477 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x08/*ALL*/, }, 478 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x2A/*ALL*/, }, 479 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x80/*ALL*/, }, 480 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x08/*ALL*/, }, 481 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, }, 482 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x10/*ALL*/, }, 483 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0xC0/*ALL*/, }, 484 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, }, 485 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x23/*ALL*/, }, 486 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x12/*ALL*/, }, 487 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0xC0/*ALL*/, }, 488 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x0A/*ALL*/, }, 489 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0xC6/*ALL*/, }, 490 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x78/*ALL*/, }, 491 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x43/*ALL*/, }, 492 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x1F/*ALL*/, }, 493 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0x53/*ALL*/, }, 494 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0xA3/*ALL*/, }, 495 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0xF0/*ALL*/, }, 496 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x8E/*ALL*/, }, 497 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xF1/*ALL*/, }, 498 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x1C/*ALL*/, }, 499 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, }, 500 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x18/*ALL*/, }, 501 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x02/*ALL*/, }, 502 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x38/*ALL*/, }, 503 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x14/*ALL*/, }, 504 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x02/*ALL*/, }, 505 { DRV_MACROVISION_REG(REG_TABLE_END) , 0x00, 0x00, } 506 }; 507 508 //**************************************************** 509 // MACROVISION MACROVISION_PAL_TYPE1_2_3_TTX 510 //**************************************************** 511 MS_U8 MST_MACROVISION_MACROVISION_PAL_TYPE1_2_3_TTX_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_PAL_TYPE1_2_3_TTX_MACROVISION_NUMS]= 512 { // Reg Mask Value 513 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x36/*ALL*/, }, 514 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x00/*ALL*/, }, 515 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1A/*ALL*/, }, 516 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x80/*ALL*/, }, 517 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x08/*ALL*/, }, 518 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x2A/*ALL*/, }, 519 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x80/*ALL*/, }, 520 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x08/*ALL*/, }, 521 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, }, 522 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x10/*ALL*/, }, 523 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xC0, 0x00/*ALL*/, }, 524 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, }, 525 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1C/*ALL*/, }, 526 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x3D/*ALL*/, }, 527 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, }, 528 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, }, 529 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0x00/*ALL*/, }, 530 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, }, 531 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x54/*ALL*/, }, 532 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x01/*ALL*/, }, 533 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0xFE/*ALL*/, }, 534 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x7E/*ALL*/, }, 535 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, }, 536 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x9D/*ALL*/, }, 537 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xDC/*ALL*/, }, 538 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x20/*ALL*/, }, 539 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, }, 540 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, }, 541 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x07/*ALL*/, }, 542 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x50/*ALL*/, }, 543 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x15/*ALL*/, }, 544 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x00/*ALL*/, }, 545 { DRV_MACROVISION_REG(REG_TABLE_END) , 0x00, 0x00, } 546 }; 547 548 //**************************************************** 549 // MACROVISION MACROVISION_PAL_TEST_P01_TTX 550 //**************************************************** 551 MS_U8 MST_MACROVISION_MACROVISION_PAL_TEST_P01_TTX_MACROVISION_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+VE_TAB_MACROVISION_PAL_TEST_P01_TTX_MACROVISION_NUMS]= 552 { // Reg Mask Value 553 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0xFF, 0x3E/*ALL*/, }, 554 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7E_L), 0x01, 0x01/*ALL*/, }, 555 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0x3F, 0x1A/*ALL*/, }, 556 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_L), 0xC0, 0x80/*ALL*/, }, 557 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_01_H), 0x0F, 0x08/*ALL*/, }, 558 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0x3F, 0x2A/*ALL*/, }, 559 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_L), 0xC0, 0x80/*ALL*/, }, 560 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_02_H), 0x0F, 0x08/*ALL*/, }, 561 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x07, 0x05/*ALL*/, }, 562 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0x38, 0x10/*ALL*/, }, 563 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_03_L), 0xE0, 0x00/*ALL*/, }, 564 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_L), 0x00, 0x00/*ALL*/, }, 565 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_78_H), 0x3F, 0x1C/*ALL*/, }, 566 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0x3F, 0x3D/*ALL*/, }, 567 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_L), 0xC0, 0x00/*ALL*/, }, 568 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_79_H), 0x0F, 0x05/*ALL*/, }, 569 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_L), 0xFF, 0x00/*ALL*/, }, 570 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7A_H), 0x7F, 0x03/*ALL*/, }, 571 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_L), 0xFF, 0x54/*ALL*/, }, 572 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7B_H), 0x7F, 0x01/*ALL*/, }, 573 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_L), 0xFF, 0xFE/*ALL*/, }, 574 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7C_H), 0xFF, 0x7E/*ALL*/, }, 575 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_L), 0xFF, 0x60/*ALL*/, }, 576 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_L), 0xFF, 0x9D/*ALL*/, }, 577 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7F_H), 0xFF, 0xDC/*ALL*/, }, 578 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x7F, 0x20/*ALL*/, }, 579 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_L), 0x80, 0x00/*ALL*/, }, 580 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_00_H), 0x3F, 0x00/*ALL*/, }, 581 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0x07, 0x07/*ALL*/, }, 582 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_L), 0xF8, 0x50/*ALL*/, }, 583 { DRV_MACROVISION_REG(REG_TC_VE_ENC2_04_H), 0x1F, 0x15/*ALL*/, }, 584 { DRV_MACROVISION_REG(REG_TC_VE_ENC1_7D_H), 0x02, 0x02/*ALL*/, }, 585 { DRV_MACROVISION_REG(REG_TABLE_END) , 0x00, 0x00, } 586 }; 587 588 MACROVISION_TAB_INFO MACROVISIONMAP_Main[MACROVISION_TYPE_NUMS]= 589 { 590 { 591 *MST_MACROVISION_MACROVISION_NTSC_TYPE1_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION, 592 }, 593 { 594 *MST_MACROVISION_MACROVISION_NTSC_TYPE2_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION, 595 }, 596 { 597 *MST_MACROVISION_MACROVISION_NTSC_TYPE3_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION, 598 }, 599 { 600 *MST_MACROVISION_MACROVISION_NTSC_TEST_N01_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION, 601 }, 602 { 603 *MST_MACROVISION_MACROVISION_NTSC_TEST_N02_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION, 604 }, 605 { 606 *MST_MACROVISION_MACROVISION_NTSC_TYPE2_TTX_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION, 607 }, 608 { 609 *MST_MACROVISION_MACROVISION_NTSC_TEST_N01_TTX_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION, 610 }, 611 { 612 *MST_MACROVISION_MACROVISION_PAL_TYPE1_2_3_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION, 613 }, 614 { 615 *MST_MACROVISION_MACROVISION_PAL_TEST_P01_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION, 616 }, 617 { 618 *MST_MACROVISION_MACROVISION_PAL_TEST_P02_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION, 619 }, 620 { 621 *MST_MACROVISION_MACROVISION_PAL_TYPE1_2_3_TTX_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION, 622 }, 623 { 624 *MST_MACROVISION_MACROVISION_PAL_TEST_P01_TTX_MACROVISION_TBL, MACROVISION_TABTYPE_MACROVISION, 625 }, 626 }; 627 628 #endif 629