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Searched refs:REG_SCDC2_BASE (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_pm_sleep.h405 #define REG_PM_SCDC2_00_L (REG_SCDC2_BASE + 0x00)
406 #define REG_PM_SCDC2_00_H (REG_SCDC2_BASE + 0x01)
407 #define REG_PM_SCDC2_01_L (REG_SCDC2_BASE + 0x02)
408 #define REG_PM_SCDC2_01_H (REG_SCDC2_BASE + 0x03)
409 #define REG_PM_SCDC2_02_L (REG_SCDC2_BASE + 0x04)
410 #define REG_PM_SCDC2_02_H (REG_SCDC2_BASE + 0x05)
411 #define REG_PM_SCDC2_03_L (REG_SCDC2_BASE + 0x06)
412 #define REG_PM_SCDC2_03_H (REG_SCDC2_BASE + 0x07)
413 #define REG_PM_SCDC2_04_L (REG_SCDC2_BASE + 0x08)
414 #define REG_PM_SCDC2_04_H (REG_SCDC2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h541 #define REG_SCDC2_BASE 0x010400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_pm_sleep.h405 #define REG_PM_SCDC2_00_L (REG_SCDC2_BASE + 0x00)
406 #define REG_PM_SCDC2_00_H (REG_SCDC2_BASE + 0x01)
407 #define REG_PM_SCDC2_01_L (REG_SCDC2_BASE + 0x02)
408 #define REG_PM_SCDC2_01_H (REG_SCDC2_BASE + 0x03)
409 #define REG_PM_SCDC2_02_L (REG_SCDC2_BASE + 0x04)
410 #define REG_PM_SCDC2_02_H (REG_SCDC2_BASE + 0x05)
411 #define REG_PM_SCDC2_03_L (REG_SCDC2_BASE + 0x06)
412 #define REG_PM_SCDC2_03_H (REG_SCDC2_BASE + 0x07)
413 #define REG_PM_SCDC2_04_L (REG_SCDC2_BASE + 0x08)
414 #define REG_PM_SCDC2_04_H (REG_SCDC2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h505 #define REG_SCDC2_BASE 0x010400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_pm_sleep.h406 #define REG_PM_SCDC2_00_L (REG_SCDC2_BASE + 0x00)
407 #define REG_PM_SCDC2_00_H (REG_SCDC2_BASE + 0x01)
408 #define REG_PM_SCDC2_01_L (REG_SCDC2_BASE + 0x02)
409 #define REG_PM_SCDC2_01_H (REG_SCDC2_BASE + 0x03)
410 #define REG_PM_SCDC2_02_L (REG_SCDC2_BASE + 0x04)
411 #define REG_PM_SCDC2_02_H (REG_SCDC2_BASE + 0x05)
412 #define REG_PM_SCDC2_03_L (REG_SCDC2_BASE + 0x06)
413 #define REG_PM_SCDC2_03_H (REG_SCDC2_BASE + 0x07)
414 #define REG_PM_SCDC2_04_L (REG_SCDC2_BASE + 0x08)
415 #define REG_PM_SCDC2_04_H (REG_SCDC2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h485 #define REG_SCDC2_BASE REG_SCDC0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_pm_sleep.h405 #define REG_PM_SCDC2_00_L (REG_SCDC2_BASE + 0x00)
406 #define REG_PM_SCDC2_00_H (REG_SCDC2_BASE + 0x01)
407 #define REG_PM_SCDC2_01_L (REG_SCDC2_BASE + 0x02)
408 #define REG_PM_SCDC2_01_H (REG_SCDC2_BASE + 0x03)
409 #define REG_PM_SCDC2_02_L (REG_SCDC2_BASE + 0x04)
410 #define REG_PM_SCDC2_02_H (REG_SCDC2_BASE + 0x05)
411 #define REG_PM_SCDC2_03_L (REG_SCDC2_BASE + 0x06)
412 #define REG_PM_SCDC2_03_H (REG_SCDC2_BASE + 0x07)
413 #define REG_PM_SCDC2_04_L (REG_SCDC2_BASE + 0x08)
414 #define REG_PM_SCDC2_04_H (REG_SCDC2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h449 #define REG_SCDC2_BASE 0x010400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_pm_sleep.h405 #define REG_PM_SCDC2_00_L (REG_SCDC2_BASE + 0x00)
406 #define REG_PM_SCDC2_00_H (REG_SCDC2_BASE + 0x01)
407 #define REG_PM_SCDC2_01_L (REG_SCDC2_BASE + 0x02)
408 #define REG_PM_SCDC2_01_H (REG_SCDC2_BASE + 0x03)
409 #define REG_PM_SCDC2_02_L (REG_SCDC2_BASE + 0x04)
410 #define REG_PM_SCDC2_02_H (REG_SCDC2_BASE + 0x05)
411 #define REG_PM_SCDC2_03_L (REG_SCDC2_BASE + 0x06)
412 #define REG_PM_SCDC2_03_H (REG_SCDC2_BASE + 0x07)
413 #define REG_PM_SCDC2_04_L (REG_SCDC2_BASE + 0x08)
414 #define REG_PM_SCDC2_04_H (REG_SCDC2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h537 #define REG_SCDC2_BASE 0x010400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_pm_sleep.h406 #define REG_PM_SCDC2_00_L (REG_SCDC2_BASE + 0x00)
407 #define REG_PM_SCDC2_00_H (REG_SCDC2_BASE + 0x01)
408 #define REG_PM_SCDC2_01_L (REG_SCDC2_BASE + 0x02)
409 #define REG_PM_SCDC2_01_H (REG_SCDC2_BASE + 0x03)
410 #define REG_PM_SCDC2_02_L (REG_SCDC2_BASE + 0x04)
411 #define REG_PM_SCDC2_02_H (REG_SCDC2_BASE + 0x05)
412 #define REG_PM_SCDC2_03_L (REG_SCDC2_BASE + 0x06)
413 #define REG_PM_SCDC2_03_H (REG_SCDC2_BASE + 0x07)
414 #define REG_PM_SCDC2_04_L (REG_SCDC2_BASE + 0x08)
415 #define REG_PM_SCDC2_04_H (REG_SCDC2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h493 #define REG_SCDC2_BASE REG_SCDC0_BASE macro
H A Dmhal_xc_chip_config.h.0492 #define REG_SCDC2_BASE REG_SCDC0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_pm_sleep.h406 #define REG_PM_SCDC2_00_L (REG_SCDC2_BASE + 0x00)
407 #define REG_PM_SCDC2_00_H (REG_SCDC2_BASE + 0x01)
408 #define REG_PM_SCDC2_01_L (REG_SCDC2_BASE + 0x02)
409 #define REG_PM_SCDC2_01_H (REG_SCDC2_BASE + 0x03)
410 #define REG_PM_SCDC2_02_L (REG_SCDC2_BASE + 0x04)
411 #define REG_PM_SCDC2_02_H (REG_SCDC2_BASE + 0x05)
412 #define REG_PM_SCDC2_03_L (REG_SCDC2_BASE + 0x06)
413 #define REG_PM_SCDC2_03_H (REG_SCDC2_BASE + 0x07)
414 #define REG_PM_SCDC2_04_L (REG_SCDC2_BASE + 0x08)
415 #define REG_PM_SCDC2_04_H (REG_SCDC2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h491 #define REG_SCDC2_BASE REG_SCDC0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_pm_sleep.h405 #define REG_PM_SCDC2_00_L (REG_SCDC2_BASE + 0x00)
406 #define REG_PM_SCDC2_00_H (REG_SCDC2_BASE + 0x01)
407 #define REG_PM_SCDC2_01_L (REG_SCDC2_BASE + 0x02)
408 #define REG_PM_SCDC2_01_H (REG_SCDC2_BASE + 0x03)
409 #define REG_PM_SCDC2_02_L (REG_SCDC2_BASE + 0x04)
410 #define REG_PM_SCDC2_02_H (REG_SCDC2_BASE + 0x05)
411 #define REG_PM_SCDC2_03_L (REG_SCDC2_BASE + 0x06)
412 #define REG_PM_SCDC2_03_H (REG_SCDC2_BASE + 0x07)
413 #define REG_PM_SCDC2_04_L (REG_SCDC2_BASE + 0x08)
414 #define REG_PM_SCDC2_04_H (REG_SCDC2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h492 #define REG_SCDC2_BASE 0x010400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_pm_sleep.h406 #define REG_PM_SCDC2_00_L (REG_SCDC2_BASE + 0x00)
407 #define REG_PM_SCDC2_00_H (REG_SCDC2_BASE + 0x01)
408 #define REG_PM_SCDC2_01_L (REG_SCDC2_BASE + 0x02)
409 #define REG_PM_SCDC2_01_H (REG_SCDC2_BASE + 0x03)
410 #define REG_PM_SCDC2_02_L (REG_SCDC2_BASE + 0x04)
411 #define REG_PM_SCDC2_02_H (REG_SCDC2_BASE + 0x05)
412 #define REG_PM_SCDC2_03_L (REG_SCDC2_BASE + 0x06)
413 #define REG_PM_SCDC2_03_H (REG_SCDC2_BASE + 0x07)
414 #define REG_PM_SCDC2_04_L (REG_SCDC2_BASE + 0x08)
415 #define REG_PM_SCDC2_04_H (REG_SCDC2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h491 #define REG_SCDC2_BASE REG_SCDC0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_pm_sleep.h405 #define REG_PM_SCDC2_00_L (REG_SCDC2_BASE + 0x00)
406 #define REG_PM_SCDC2_00_H (REG_SCDC2_BASE + 0x01)
407 #define REG_PM_SCDC2_01_L (REG_SCDC2_BASE + 0x02)
408 #define REG_PM_SCDC2_01_H (REG_SCDC2_BASE + 0x03)
409 #define REG_PM_SCDC2_02_L (REG_SCDC2_BASE + 0x04)
410 #define REG_PM_SCDC2_02_H (REG_SCDC2_BASE + 0x05)
411 #define REG_PM_SCDC2_03_L (REG_SCDC2_BASE + 0x06)
412 #define REG_PM_SCDC2_03_H (REG_SCDC2_BASE + 0x07)
413 #define REG_PM_SCDC2_04_L (REG_SCDC2_BASE + 0x08)
414 #define REG_PM_SCDC2_04_H (REG_SCDC2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h555 #define REG_SCDC2_BASE 0x010400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_pm_sleep.h405 #define REG_PM_SCDC2_00_L (REG_SCDC2_BASE + 0x00)
406 #define REG_PM_SCDC2_00_H (REG_SCDC2_BASE + 0x01)
407 #define REG_PM_SCDC2_01_L (REG_SCDC2_BASE + 0x02)
408 #define REG_PM_SCDC2_01_H (REG_SCDC2_BASE + 0x03)
409 #define REG_PM_SCDC2_02_L (REG_SCDC2_BASE + 0x04)
410 #define REG_PM_SCDC2_02_H (REG_SCDC2_BASE + 0x05)
411 #define REG_PM_SCDC2_03_L (REG_SCDC2_BASE + 0x06)
412 #define REG_PM_SCDC2_03_H (REG_SCDC2_BASE + 0x07)
413 #define REG_PM_SCDC2_04_L (REG_SCDC2_BASE + 0x08)
414 #define REG_PM_SCDC2_04_H (REG_SCDC2_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h550 #define REG_SCDC2_BASE 0x010400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h467 #define REG_SCDC2_BASE 0x010400UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h465 #define REG_SCDC2_BASE 0x010400UL macro