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Searched refs:REG_SCDC1_BASE (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_pm_sleep.h383 #define REG_PM_SCDC1_00_L (REG_SCDC1_BASE + 0x00)
384 #define REG_PM_SCDC1_00_H (REG_SCDC1_BASE + 0x01)
385 #define REG_PM_SCDC1_01_L (REG_SCDC1_BASE + 0x02)
386 #define REG_PM_SCDC1_01_H (REG_SCDC1_BASE + 0x03)
387 #define REG_PM_SCDC1_02_L (REG_SCDC1_BASE + 0x04)
388 #define REG_PM_SCDC1_02_H (REG_SCDC1_BASE + 0x05)
389 #define REG_PM_SCDC1_03_L (REG_SCDC1_BASE + 0x06)
390 #define REG_PM_SCDC1_03_H (REG_SCDC1_BASE + 0x07)
391 #define REG_PM_SCDC1_04_L (REG_SCDC1_BASE + 0x08)
392 #define REG_PM_SCDC1_04_H (REG_SCDC1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h540 #define REG_SCDC1_BASE 0x010300UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_pm_sleep.h383 #define REG_PM_SCDC1_00_L (REG_SCDC1_BASE + 0x00)
384 #define REG_PM_SCDC1_00_H (REG_SCDC1_BASE + 0x01)
385 #define REG_PM_SCDC1_01_L (REG_SCDC1_BASE + 0x02)
386 #define REG_PM_SCDC1_01_H (REG_SCDC1_BASE + 0x03)
387 #define REG_PM_SCDC1_02_L (REG_SCDC1_BASE + 0x04)
388 #define REG_PM_SCDC1_02_H (REG_SCDC1_BASE + 0x05)
389 #define REG_PM_SCDC1_03_L (REG_SCDC1_BASE + 0x06)
390 #define REG_PM_SCDC1_03_H (REG_SCDC1_BASE + 0x07)
391 #define REG_PM_SCDC1_04_L (REG_SCDC1_BASE + 0x08)
392 #define REG_PM_SCDC1_04_H (REG_SCDC1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h504 #define REG_SCDC1_BASE 0x010300UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_pm_sleep.h384 #define REG_PM_SCDC1_00_L (REG_SCDC1_BASE + 0x00)
385 #define REG_PM_SCDC1_00_H (REG_SCDC1_BASE + 0x01)
386 #define REG_PM_SCDC1_01_L (REG_SCDC1_BASE + 0x02)
387 #define REG_PM_SCDC1_01_H (REG_SCDC1_BASE + 0x03)
388 #define REG_PM_SCDC1_02_L (REG_SCDC1_BASE + 0x04)
389 #define REG_PM_SCDC1_02_H (REG_SCDC1_BASE + 0x05)
390 #define REG_PM_SCDC1_03_L (REG_SCDC1_BASE + 0x06)
391 #define REG_PM_SCDC1_03_H (REG_SCDC1_BASE + 0x07)
392 #define REG_PM_SCDC1_04_L (REG_SCDC1_BASE + 0x08)
393 #define REG_PM_SCDC1_04_H (REG_SCDC1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h484 #define REG_SCDC1_BASE REG_SCDC0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_pm_sleep.h383 #define REG_PM_SCDC1_00_L (REG_SCDC1_BASE + 0x00)
384 #define REG_PM_SCDC1_00_H (REG_SCDC1_BASE + 0x01)
385 #define REG_PM_SCDC1_01_L (REG_SCDC1_BASE + 0x02)
386 #define REG_PM_SCDC1_01_H (REG_SCDC1_BASE + 0x03)
387 #define REG_PM_SCDC1_02_L (REG_SCDC1_BASE + 0x04)
388 #define REG_PM_SCDC1_02_H (REG_SCDC1_BASE + 0x05)
389 #define REG_PM_SCDC1_03_L (REG_SCDC1_BASE + 0x06)
390 #define REG_PM_SCDC1_03_H (REG_SCDC1_BASE + 0x07)
391 #define REG_PM_SCDC1_04_L (REG_SCDC1_BASE + 0x08)
392 #define REG_PM_SCDC1_04_H (REG_SCDC1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h448 #define REG_SCDC1_BASE 0x010300UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_pm_sleep.h383 #define REG_PM_SCDC1_00_L (REG_SCDC1_BASE + 0x00)
384 #define REG_PM_SCDC1_00_H (REG_SCDC1_BASE + 0x01)
385 #define REG_PM_SCDC1_01_L (REG_SCDC1_BASE + 0x02)
386 #define REG_PM_SCDC1_01_H (REG_SCDC1_BASE + 0x03)
387 #define REG_PM_SCDC1_02_L (REG_SCDC1_BASE + 0x04)
388 #define REG_PM_SCDC1_02_H (REG_SCDC1_BASE + 0x05)
389 #define REG_PM_SCDC1_03_L (REG_SCDC1_BASE + 0x06)
390 #define REG_PM_SCDC1_03_H (REG_SCDC1_BASE + 0x07)
391 #define REG_PM_SCDC1_04_L (REG_SCDC1_BASE + 0x08)
392 #define REG_PM_SCDC1_04_H (REG_SCDC1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h536 #define REG_SCDC1_BASE 0x010300UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_pm_sleep.h384 #define REG_PM_SCDC1_00_L (REG_SCDC1_BASE + 0x00)
385 #define REG_PM_SCDC1_00_H (REG_SCDC1_BASE + 0x01)
386 #define REG_PM_SCDC1_01_L (REG_SCDC1_BASE + 0x02)
387 #define REG_PM_SCDC1_01_H (REG_SCDC1_BASE + 0x03)
388 #define REG_PM_SCDC1_02_L (REG_SCDC1_BASE + 0x04)
389 #define REG_PM_SCDC1_02_H (REG_SCDC1_BASE + 0x05)
390 #define REG_PM_SCDC1_03_L (REG_SCDC1_BASE + 0x06)
391 #define REG_PM_SCDC1_03_H (REG_SCDC1_BASE + 0x07)
392 #define REG_PM_SCDC1_04_L (REG_SCDC1_BASE + 0x08)
393 #define REG_PM_SCDC1_04_H (REG_SCDC1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h492 #define REG_SCDC1_BASE REG_SCDC0_BASE macro
H A Dmhal_xc_chip_config.h.0491 #define REG_SCDC1_BASE REG_SCDC0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_pm_sleep.h384 #define REG_PM_SCDC1_00_L (REG_SCDC1_BASE + 0x00)
385 #define REG_PM_SCDC1_00_H (REG_SCDC1_BASE + 0x01)
386 #define REG_PM_SCDC1_01_L (REG_SCDC1_BASE + 0x02)
387 #define REG_PM_SCDC1_01_H (REG_SCDC1_BASE + 0x03)
388 #define REG_PM_SCDC1_02_L (REG_SCDC1_BASE + 0x04)
389 #define REG_PM_SCDC1_02_H (REG_SCDC1_BASE + 0x05)
390 #define REG_PM_SCDC1_03_L (REG_SCDC1_BASE + 0x06)
391 #define REG_PM_SCDC1_03_H (REG_SCDC1_BASE + 0x07)
392 #define REG_PM_SCDC1_04_L (REG_SCDC1_BASE + 0x08)
393 #define REG_PM_SCDC1_04_H (REG_SCDC1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h490 #define REG_SCDC1_BASE REG_SCDC0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_pm_sleep.h383 #define REG_PM_SCDC1_00_L (REG_SCDC1_BASE + 0x00)
384 #define REG_PM_SCDC1_00_H (REG_SCDC1_BASE + 0x01)
385 #define REG_PM_SCDC1_01_L (REG_SCDC1_BASE + 0x02)
386 #define REG_PM_SCDC1_01_H (REG_SCDC1_BASE + 0x03)
387 #define REG_PM_SCDC1_02_L (REG_SCDC1_BASE + 0x04)
388 #define REG_PM_SCDC1_02_H (REG_SCDC1_BASE + 0x05)
389 #define REG_PM_SCDC1_03_L (REG_SCDC1_BASE + 0x06)
390 #define REG_PM_SCDC1_03_H (REG_SCDC1_BASE + 0x07)
391 #define REG_PM_SCDC1_04_L (REG_SCDC1_BASE + 0x08)
392 #define REG_PM_SCDC1_04_H (REG_SCDC1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h491 #define REG_SCDC1_BASE 0x010300UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_pm_sleep.h384 #define REG_PM_SCDC1_00_L (REG_SCDC1_BASE + 0x00)
385 #define REG_PM_SCDC1_00_H (REG_SCDC1_BASE + 0x01)
386 #define REG_PM_SCDC1_01_L (REG_SCDC1_BASE + 0x02)
387 #define REG_PM_SCDC1_01_H (REG_SCDC1_BASE + 0x03)
388 #define REG_PM_SCDC1_02_L (REG_SCDC1_BASE + 0x04)
389 #define REG_PM_SCDC1_02_H (REG_SCDC1_BASE + 0x05)
390 #define REG_PM_SCDC1_03_L (REG_SCDC1_BASE + 0x06)
391 #define REG_PM_SCDC1_03_H (REG_SCDC1_BASE + 0x07)
392 #define REG_PM_SCDC1_04_L (REG_SCDC1_BASE + 0x08)
393 #define REG_PM_SCDC1_04_H (REG_SCDC1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h490 #define REG_SCDC1_BASE REG_SCDC0_BASE macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_pm_sleep.h383 #define REG_PM_SCDC1_00_L (REG_SCDC1_BASE + 0x00)
384 #define REG_PM_SCDC1_00_H (REG_SCDC1_BASE + 0x01)
385 #define REG_PM_SCDC1_01_L (REG_SCDC1_BASE + 0x02)
386 #define REG_PM_SCDC1_01_H (REG_SCDC1_BASE + 0x03)
387 #define REG_PM_SCDC1_02_L (REG_SCDC1_BASE + 0x04)
388 #define REG_PM_SCDC1_02_H (REG_SCDC1_BASE + 0x05)
389 #define REG_PM_SCDC1_03_L (REG_SCDC1_BASE + 0x06)
390 #define REG_PM_SCDC1_03_H (REG_SCDC1_BASE + 0x07)
391 #define REG_PM_SCDC1_04_L (REG_SCDC1_BASE + 0x08)
392 #define REG_PM_SCDC1_04_H (REG_SCDC1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h554 #define REG_SCDC1_BASE 0x010300UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_pm_sleep.h383 #define REG_PM_SCDC1_00_L (REG_SCDC1_BASE + 0x00)
384 #define REG_PM_SCDC1_00_H (REG_SCDC1_BASE + 0x01)
385 #define REG_PM_SCDC1_01_L (REG_SCDC1_BASE + 0x02)
386 #define REG_PM_SCDC1_01_H (REG_SCDC1_BASE + 0x03)
387 #define REG_PM_SCDC1_02_L (REG_SCDC1_BASE + 0x04)
388 #define REG_PM_SCDC1_02_H (REG_SCDC1_BASE + 0x05)
389 #define REG_PM_SCDC1_03_L (REG_SCDC1_BASE + 0x06)
390 #define REG_PM_SCDC1_03_H (REG_SCDC1_BASE + 0x07)
391 #define REG_PM_SCDC1_04_L (REG_SCDC1_BASE + 0x08)
392 #define REG_PM_SCDC1_04_H (REG_SCDC1_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h549 #define REG_SCDC1_BASE 0x010300UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h466 #define REG_SCDC1_BASE 0x010300UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h464 #define REG_SCDC1_BASE 0x010300UL macro