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Searched refs:REG_SCDC0_BASE (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_pm_sleep.h361 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00)
362 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01)
363 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02)
364 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03)
365 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04)
366 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05)
367 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06)
368 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07)
369 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08)
370 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h465 #define REG_SCDC0_BASE 0x010200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_pm_sleep.h361 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00)
362 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01)
363 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02)
364 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03)
365 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04)
366 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05)
367 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06)
368 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07)
369 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08)
370 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_pm_sleep.h361 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00)
362 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01)
363 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02)
364 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03)
365 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04)
366 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05)
367 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06)
368 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07)
369 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08)
370 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h503 #define REG_SCDC0_BASE 0x010200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_pm_sleep.h362 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00)
363 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01)
364 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02)
365 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03)
366 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04)
367 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05)
368 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06)
369 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07)
370 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08)
371 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h483 #define REG_SCDC0_BASE 0x010700UL macro
484 #define REG_SCDC1_BASE REG_SCDC0_BASE
485 #define REG_SCDC2_BASE REG_SCDC0_BASE
486 #define REG_SCDC3_BASE REG_SCDC0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_pm_sleep.h361 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00)
362 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01)
363 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02)
364 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03)
365 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04)
366 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05)
367 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06)
368 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07)
369 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08)
370 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h447 #define REG_SCDC0_BASE 0x010200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_pm_sleep.h361 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00)
362 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01)
363 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02)
364 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03)
365 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04)
366 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05)
367 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06)
368 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07)
369 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08)
370 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h535 #define REG_SCDC0_BASE 0x010200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_pm_sleep.h362 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00)
363 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01)
364 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02)
365 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03)
366 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04)
367 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05)
368 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06)
369 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07)
370 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08)
371 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h491 #define REG_SCDC0_BASE 0x010700UL macro
492 #define REG_SCDC1_BASE REG_SCDC0_BASE
493 #define REG_SCDC2_BASE REG_SCDC0_BASE
494 #define REG_SCDC3_BASE REG_SCDC0_BASE
H A Dmhal_xc_chip_config.h.0490 #define REG_SCDC0_BASE 0x010700UL
491 #define REG_SCDC1_BASE REG_SCDC0_BASE
492 #define REG_SCDC2_BASE REG_SCDC0_BASE
493 #define REG_SCDC3_BASE REG_SCDC0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_pm_sleep.h362 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00)
363 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01)
364 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02)
365 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03)
366 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04)
367 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05)
368 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06)
369 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07)
370 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08)
371 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h489 #define REG_SCDC0_BASE 0x010700UL macro
490 #define REG_SCDC1_BASE REG_SCDC0_BASE
491 #define REG_SCDC2_BASE REG_SCDC0_BASE
492 #define REG_SCDC3_BASE REG_SCDC0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_pm_sleep.h361 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00)
362 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01)
363 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02)
364 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03)
365 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04)
366 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05)
367 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06)
368 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07)
369 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08)
370 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h490 #define REG_SCDC0_BASE 0x010200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_pm_sleep.h362 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00)
363 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01)
364 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02)
365 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03)
366 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04)
367 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05)
368 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06)
369 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07)
370 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08)
371 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h489 #define REG_SCDC0_BASE 0x010700UL macro
490 #define REG_SCDC1_BASE REG_SCDC0_BASE
491 #define REG_SCDC2_BASE REG_SCDC0_BASE
492 #define REG_SCDC3_BASE REG_SCDC0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_pm_sleep.h361 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00)
362 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01)
363 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02)
364 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03)
365 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04)
366 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05)
367 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06)
368 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07)
369 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08)
370 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h553 #define REG_SCDC0_BASE 0x010200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_pm_sleep.h361 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00)
362 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01)
363 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02)
364 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03)
365 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04)
366 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05)
367 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06)
368 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07)
369 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08)
370 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h548 #define REG_SCDC0_BASE 0x010200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h463 #define REG_SCDC0_BASE 0x010200UL macro

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