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Searched refs:REG_MVOP_BASE (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h497 #define REG_MVOP_BASE 0x101400UL macro
760 #define REG_MVOP_FORCE_WR (REG_MVOP_BASE + 0x27)
762 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
763 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x40)
764 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x41)
765 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x42)
766 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x43)
768 #define REG_MVOP_SKIPSIZE (REG_MVOP_BASE + 0x44)
769 #define REG_MVOP_VOFFSET0 (REG_MVOP_BASE + 0x45)
770 #define REG_MVOP_VOFFSET1 (REG_MVOP_BASE + 0x46)
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h495 #define REG_MVOP_BASE 0x101400UL macro
758 #define REG_MVOP_FORCE_WR (REG_MVOP_BASE + 0x27)
760 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
761 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x40)
762 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x41)
763 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x42)
764 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x43)
766 #define REG_MVOP_SKIPSIZE (REG_MVOP_BASE + 0x44)
767 #define REG_MVOP_VOFFSET0 (REG_MVOP_BASE + 0x45)
768 #define REG_MVOP_VOFFSET1 (REG_MVOP_BASE + 0x46)
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h509 #define REG_MVOP_BASE 0x101400UL macro
610 #define REG_MVOP_HSK (REG_MVOP_BASE + 0x7C)
612 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80)
613 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82)
614 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84)
615 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86)
939 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h515 #define REG_MVOP_BASE 0x101400UL macro
616 #define REG_MVOP_HSK (REG_MVOP_BASE + 0x7C)
618 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80)
619 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82)
620 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84)
621 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86)
945 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h515 #define REG_MVOP_BASE 0x101400UL macro
616 #define REG_MVOP_HSK (REG_MVOP_BASE + 0x7C)
618 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80)
619 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82)
620 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84)
621 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86)
938 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h517 #define REG_MVOP_BASE 0x101400UL macro
618 #define REG_MVOP_HSK (REG_MVOP_BASE + 0x7C)
620 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80)
621 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82)
622 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84)
623 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86)
932 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
H A Dmhal_xc_chip_config.h.0516 #define REG_MVOP_BASE 0x101400UL
617 #define REG_MVOP_HSK (REG_MVOP_BASE + 0x7C)
619 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80)
620 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82)
621 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84)
622 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86)
931 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h524 #define REG_MVOP_BASE 0x101400UL macro
867 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
868 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80)
869 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82)
870 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84)
871 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86)
872 #define REG_MVOP_4K2K_60_2P (REG_MVOP_BASE + (0x53<<1))
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h478 #define REG_MVOP_BASE 0x101400UL macro
812 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
813 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x40)
814 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x41)
815 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x42)
816 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x43)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h569 #define REG_MVOP_BASE 0x101400UL macro
920 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
921 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80)
922 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82)
923 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84)
924 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86)
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h537 #define REG_MVOP_BASE 0x101400UL macro
880 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
881 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x40)
882 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x41)
883 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x42)
884 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x43)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h582 #define REG_MVOP_BASE 0x101400UL macro
932 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
933 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80)
934 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82)
935 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84)
936 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86)
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h587 #define REG_MVOP_BASE 0x101400UL macro
937 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
938 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80)
939 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82)
940 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84)
941 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86)
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h573 #define REG_MVOP_BASE 0x101400UL macro
924 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
925 #define REG_MVOP_CROP_H_START (REG_MVOP_BASE + 0x80)
926 #define REG_MVOP_CROP_V_START (REG_MVOP_BASE + 0x82)
927 #define REG_MVOP_CROP_H_SIZE (REG_MVOP_BASE + 0x84)
928 #define REG_MVOP_CROP_V_SIZE (REG_MVOP_BASE + 0x86)
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h402 #define REG_MVOP_BASE 0x101400 macro
645 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h402 #define REG_MVOP_BASE 0x101400 macro
645 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76)
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_sc.c1660 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x80), stCropInfo.u16XStart, 0x1fff); in Hal_SC_sw_db()
1661 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x82), stCropInfo.u16YStart, 0x1fff); in Hal_SC_sw_db()
1662 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x84), stCropInfo.u16XSize, 0x1fff); in Hal_SC_sw_db()
1663 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x86), stCropInfo.u16YSize, 0x1fff); in Hal_SC_sw_db()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_sc.c1573 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x80), stCropInfo.u16XStart, 0x1fff); in Hal_SC_sw_db()
1574 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x82), stCropInfo.u16YStart, 0x1fff); in Hal_SC_sw_db()
1575 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x84), stCropInfo.u16XSize, 0x1fff); in Hal_SC_sw_db()
1576 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x86), stCropInfo.u16YSize, 0x1fff); in Hal_SC_sw_db()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_sc.c1656 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x80), stCropInfo.u16XStart, 0x1fff); in Hal_SC_sw_db()
1657 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x82), stCropInfo.u16YStart, 0x1fff); in Hal_SC_sw_db()
1658 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x84), stCropInfo.u16XSize, 0x1fff); in Hal_SC_sw_db()
1659 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x86), stCropInfo.u16YSize, 0x1fff); in Hal_SC_sw_db()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_sc.c1851 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x80), stCropInfo.u16XStart, 0x1fff); in Hal_SC_sw_db()
1852 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x82), stCropInfo.u16YStart, 0x1fff); in Hal_SC_sw_db()
1853 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x84), stCropInfo.u16XSize, 0x1fff); in Hal_SC_sw_db()
1854 MDrv_Write2ByteMask((REG_MVOP_BASE + 0x86), stCropInfo.u16YSize, 0x1fff); in Hal_SC_sw_db()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c2128 bVideoPmode = (MDrv_ReadRegBit((REG_MVOP_BASE + 0x22), (BIT(7)))) ? FALSE : TRUE; in HAL_XC_DIP_SetWinProperty()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c2129 bVideoPmode = (MDrv_ReadRegBit((REG_MVOP_BASE + 0x22), (BIT(7)))) ? FALSE : TRUE; in HAL_XC_DIP_SetWinProperty()