Searched refs:REG_MIU0_EX_BASE (Results 1 – 14 of 14) sorted by relevance
495 #define REG_MIU0_EX_BASE 0x161500 macro949 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)950 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26)
501 #define REG_MIU0_EX_BASE 0x161500 macro955 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)956 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26)
501 #define REG_MIU0_EX_BASE 0x161500 macro965 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)966 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26)
503 #define REG_MIU0_EX_BASE 0x161500 macro959 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)960 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26)
502 #define REG_MIU0_EX_BASE 0x161500958 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)959 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26)
458 #define REG_MIU0_EX_BASE 0x161500UL macro979 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)980 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26)
546 #define REG_MIU0_EX_BASE 0x161500UL macro1094 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)1095 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26)
514 #define REG_MIU0_EX_BASE 0x161500UL macro1049 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)1050 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26)
559 #define REG_MIU0_EX_BASE 0x161500UL macro1106 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)1107 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26)
501 #define REG_MIU0_EX_BASE 0x161500UL macro1043 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)1044 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26)
564 #define REG_MIU0_EX_BASE 0x161500UL macro1111 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)1112 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26)
550 #define REG_MIU0_EX_BASE 0x161500UL macro1098 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)1099 #define MIU0_G5_REQUEST_MASK (REG_MIU0_EX_BASE + 0x26)
477 #define REG_MIU0_EX_BASE 0x161500UL macro933 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)
475 #define REG_MIU0_EX_BASE 0x161500UL macro915 #define MIU0_G4_REQUEST_MASK (REG_MIU0_EX_BASE + 0x06)