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Searched refs:REG_MIU0_BASE (Results 1 – 25 of 61) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h386 #define REG_MIU0_BASE 0x101200 macro
651 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
652 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
653 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
654 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h386 #define REG_MIU0_BASE 0x101200 macro
651 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
652 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
653 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
654 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h476 #define REG_MIU0_BASE 0x101200UL macro
929 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
930 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
931 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
932 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h474 #define REG_MIU0_BASE 0x101200UL macro
911 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
912 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
913 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
914 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h494 #define REG_MIU0_BASE 0x101200 macro
945 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
946 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
947 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
948 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h500 #define REG_MIU0_BASE 0x101200 macro
951 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
952 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
953 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
954 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h500 #define REG_MIU0_BASE 0x101200 macro
961 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
962 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
963 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
964 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h502 #define REG_MIU0_BASE 0x101200 macro
955 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
956 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
957 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
958 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
H A Dmhal_xc_chip_config.h.0501 #define REG_MIU0_BASE 0x101200
954 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
955 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
956 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
957 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h457 #define REG_MIU0_BASE 0x101200UL macro
975 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
976 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
977 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
978 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h545 #define REG_MIU0_BASE 0x101200UL macro
1090 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
1091 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
1092 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
1093 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h513 #define REG_MIU0_BASE 0x101200UL macro
1045 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
1046 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
1047 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
1048 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h558 #define REG_MIU0_BASE 0x101200UL macro
1102 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
1103 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
1104 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
1105 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h500 #define REG_MIU0_BASE 0x101200UL macro
1039 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
1040 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
1041 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
1042 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h563 #define REG_MIU0_BASE 0x101200UL macro
1107 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
1108 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
1109 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
1110 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h549 #define REG_MIU0_BASE 0x101200UL macro
1094 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46)
1095 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66)
1096 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86)
1097 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6)
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_ld.c690 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF4, 0x0C, 0x0C); // MIU select (Group1 BIT15) in MDrv_XC_LD_Set_MIUSel()
695 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF4, 0x00, 0x0C); // MIU select (Group1 BIT15) in MDrv_XC_LD_Set_MIUSel()
701 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF0, 0x08, 0x08); // MIU select (Group1 BIT15) in MDrv_XC_LD_Set_MIUSel()
706 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF0, 0x00, 0x08); // MIU select (Group1 BIT15) in MDrv_XC_LD_Set_MIUSel()
712 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF4, 0x0C, 0x0C); // MIU select (Group1 BIT15) in MDrv_XC_LD_Set_MIUSel()
717 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF4, 0x00, 0x0C); // MIU select (Group1 BIT15) in MDrv_XC_LD_Set_MIUSel()
723 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF2, 0x40, 0x40); // MIU select (Group1 BIT15) in MDrv_XC_LD_Set_MIUSel()
728 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF2, 0x00, 0x40); // MIU select (Group1 BIT15) in MDrv_XC_LD_Set_MIUSel()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_frc.c618 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC_G0REQUEST_MASK); // MIU select (Group0) in MHal_FRC_set_miusel()
619 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
620 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC_G2REQUEST_MASK); // MIU select (Group2) in MHal_FRC_set_miusel()
621 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC_G3REQUEST_MASK); // MIU select (Group3) in MHal_FRC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_frc.c796 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC_G0REQUEST_MASK); // MIU select (Group0) in MHal_FRC_set_miusel()
797 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
798 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC_G2REQUEST_MASK); // MIU select (Group2) in MHal_FRC_set_miusel()
799 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC_G3REQUEST_MASK); // MIU select (Group3) in MHal_FRC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_frc.c779 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC_G0REQUEST_MASK); // MIU select (Group0) in MHal_FRC_set_miusel()
780 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
781 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC_G2REQUEST_MASK); // MIU select (Group2) in MHal_FRC_set_miusel()
782 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC_G3REQUEST_MASK); // MIU select (Group3) in MHal_FRC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_sc.c2316 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF3, 0x00, 0x07); in Hal_SC_set_miusel()
2323 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF3, 0x00, 0x07); in Hal_SC_set_miusel()
2329 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC0_G0REQUEST_MASK); // MIU select (Group0) in Hal_SC_set_miusel()
2330 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC0_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
2331 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC0_G2REQUEST_MASK); // MIU select (Group2) in Hal_SC_set_miusel()
2332 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC0_G3REQUEST_MASK); // MIU select (Group3) in Hal_SC_set_miusel()
2341 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC1_G0REQUEST_MASK); // MIU select (Group0) in Hal_SC_set_miusel()
2342 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC1_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
2343 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC1_G2REQUEST_MASK); // MIU select (Group2) in Hal_SC_set_miusel()
2344 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC1_G3REQUEST_MASK); // MIU select (Group3) in Hal_SC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_sc.c2229 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF3, 0x00, 0x07); in Hal_SC_set_miusel()
2236 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF3, 0x00, 0x07); in Hal_SC_set_miusel()
2242 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC0_G0REQUEST_MASK); // MIU select (Group0) in Hal_SC_set_miusel()
2243 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC0_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
2244 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC0_G2REQUEST_MASK); // MIU select (Group2) in Hal_SC_set_miusel()
2245 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC0_G3REQUEST_MASK); // MIU select (Group3) in Hal_SC_set_miusel()
2254 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC1_G0REQUEST_MASK); // MIU select (Group0) in Hal_SC_set_miusel()
2255 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC1_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
2256 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC1_G2REQUEST_MASK); // MIU select (Group2) in Hal_SC_set_miusel()
2257 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC1_G3REQUEST_MASK); // MIU select (Group3) in Hal_SC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_sc.c2326 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF3, 0x00, 0x07); in Hal_SC_set_miusel()
2333 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF3, 0x00, 0x07); in Hal_SC_set_miusel()
2339 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC0_G0REQUEST_MASK); // MIU select (Group0) in Hal_SC_set_miusel()
2340 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC0_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
2341 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC0_G2REQUEST_MASK); // MIU select (Group2) in Hal_SC_set_miusel()
2342 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC0_G3REQUEST_MASK); // MIU select (Group3) in Hal_SC_set_miusel()
2351 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC1_G0REQUEST_MASK); // MIU select (Group0) in Hal_SC_set_miusel()
2352 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC1_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
2353 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC1_G2REQUEST_MASK); // MIU select (Group2) in Hal_SC_set_miusel()
2354 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC1_G3REQUEST_MASK); // MIU select (Group3) in Hal_SC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_sc.c2527 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF3, 0x00, 0x07); in Hal_SC_set_miusel()
2534 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF3, 0x00, 0x07); in Hal_SC_set_miusel()
2540 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC0_G0REQUEST_MASK); // MIU select (Group0) in Hal_SC_set_miusel()
2541 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC0_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
2542 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC0_G2REQUEST_MASK); // MIU select (Group2) in Hal_SC_set_miusel()
2543 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC0_G3REQUEST_MASK); // MIU select (Group3) in Hal_SC_set_miusel()
2552 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC1_G0REQUEST_MASK); // MIU select (Group0) in Hal_SC_set_miusel()
2553 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC1_G1REQUEST_MASK); // MIU select (Group1) in Hal_SC_set_miusel()
2554 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC1_G2REQUEST_MASK); // MIU select (Group2) in Hal_SC_set_miusel()
2555 … MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC1_G3REQUEST_MASK); // MIU select (Group3) in Hal_SC_set_miusel()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_frc.c757 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF0), 0x00, MIU_SC_G0REQUEST_MASK); // MIU select (Group0) in MHal_FRC_set_miusel()
758 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF2), 0x00, MIU_SC_G1REQUEST_MASK); // MIU select (Group1) in MHal_FRC_set_miusel()
759 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF4), 0x00, MIU_SC_G2REQUEST_MASK); // MIU select (Group2) in MHal_FRC_set_miusel()
760 MDrv_Write2ByteMask((REG_MIU0_BASE + 0xF6), 0x00, MIU_SC_G3REQUEST_MASK); // MIU select (Group3) in MHal_FRC_set_miusel()

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