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Searched refs:REG_MIPS_C_FIQ_CLR (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A DregIRQ.h175 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x2C*2) //[IRQ][HAL][002] Clear bit … macro
244 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
270 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
294 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
317 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
341 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
364 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A DregIRQ.h175 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x2C*2) macro
244 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
270 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
294 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
317 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
341 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
364 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A DregIRQ.h175 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x2C*2) macro
244 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
270 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
294 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
317 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
341 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A DregIRQ.h175 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x2C*2) macro
244 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
270 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
294 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
317 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
341 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A DregIRQ.h175 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x2C*2) macro
244 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
270 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
294 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
317 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
341 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A DregIRQ.h175 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x2C*2) //[IRQ][HAL][002] Clear bit … macro
244 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
270 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
294 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
317 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
341 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A DregIRQ.h137 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x4C*2) macro
169 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
187 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
203 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
219 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A DregIRQ.h137 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + 0x4C*2) macro
169 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
187 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
203 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
219 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A DregIRQ.h127 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x002C << 1)) macro
159 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A DregIRQ.h127 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x002C << 1)) macro
159 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A DregIRQ.h127 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x002C << 1)) macro
159 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A DregIRQ.h135 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x4c << 1)) macro
178 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A DregIRQ.h135 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x4c << 1)) macro
178 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A DregIRQ.h135 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x4c << 1)) macro
178 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A DregIRQ.h135 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x4c << 1)) macro
178 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A DregIRQ.h135 #define REG_MIPS_C_FIQ_CLR (RIUBASE_IRQ + (0x4c << 1)) macro
178 #define REG_C_FIQ_CLR REG_MIPS_C_FIQ_CLR