| /utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/ |
| H A D | hwregMHL.h | 108 #define REG_MHL_CBUS_BANK 0x001F00UL macro
116 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
117 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
118 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
119 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
120 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
121 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
122 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
123 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
124 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/ |
| H A D | hwregMHL.h | 108 #define REG_MHL_CBUS_BANK 0x001F00UL macro
116 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
117 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
118 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
119 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
120 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
121 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
122 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
123 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
124 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/ |
| H A D | hwregMHL.h | 108 #define REG_MHL_CBUS_BANK 0x001F00UL macro
116 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
117 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
118 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
119 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
120 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
121 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
122 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
123 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
124 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/ |
| H A D | hwregMHL.h | 108 #define REG_MHL_CBUS_BANK 0x001F00UL macro
116 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
117 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
118 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
119 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
120 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
121 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
122 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
123 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
124 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/ |
| H A D | hwregMHL.h | 108 #define REG_MHL_CBUS_BANK 0x001F00UL macro
116 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
117 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
118 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
119 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
120 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
121 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
122 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
123 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
124 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/ |
| H A D | hwregMHL.h | 108 #define REG_MHL_CBUS_BANK 0x001F00UL macro
116 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
117 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
118 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
119 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
120 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
121 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
122 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
123 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
124 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/ |
| H A D | hwregMHL.h | 108 #define REG_MHL_CBUS_BANK 0x001F00UL macro
116 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
117 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
118 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
119 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
120 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
121 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
122 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
123 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
124 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/ |
| H A D | hwregMHL.h | 108 #define REG_MHL_CBUS_BANK 0x001F00UL macro
116 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
117 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
118 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
119 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
120 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
121 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
122 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
123 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
124 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/ |
| H A D | hwregMHL.h | 108 #define REG_MHL_CBUS_BANK 0x001F00UL macro
116 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
117 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
118 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
119 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
120 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
121 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
122 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
123 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
124 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_pm_sleep.h | 527 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
528 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
529 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
530 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
531 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
532 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
533 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
534 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
535 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
536 #define REG_MHL_CBUS_09 (REG_MHL_CBUS_BANK + 0x12)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_pm_sleep.h | 525 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
526 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
527 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
528 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
529 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
530 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
531 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
532 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
533 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
534 #define REG_MHL_CBUS_09 (REG_MHL_CBUS_BANK + 0x12)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_pm_sleep.h | 526 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
527 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
528 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
529 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
530 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
531 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
532 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
533 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
534 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
535 #define REG_MHL_CBUS_09 (REG_MHL_CBUS_BANK + 0x12)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_pm_sleep.h | 527 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
528 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
529 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
530 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
531 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
532 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
533 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
534 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
535 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
536 #define REG_MHL_CBUS_09 (REG_MHL_CBUS_BANK + 0x12)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_pm_sleep.h | 527 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
528 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
529 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
530 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
531 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
532 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
533 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
534 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
535 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
536 #define REG_MHL_CBUS_09 (REG_MHL_CBUS_BANK + 0x12)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_pm_sleep.h | 528 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
529 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
530 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
531 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
532 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
533 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
534 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
535 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
536 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
537 #define REG_MHL_CBUS_09 (REG_MHL_CBUS_BANK + 0x12)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_pm_sleep.h | 528 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
529 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
530 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
531 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
532 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
533 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
534 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
535 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
536 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
537 #define REG_MHL_CBUS_09 (REG_MHL_CBUS_BANK + 0x12)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_pm_sleep.h | 527 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
528 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
529 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
530 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
531 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
532 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
533 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
534 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
535 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
536 #define REG_MHL_CBUS_09 (REG_MHL_CBUS_BANK + 0x12)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_pm_sleep.h | 526 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
527 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
528 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
529 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
530 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
531 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
532 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
533 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
534 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
535 #define REG_MHL_CBUS_09 (REG_MHL_CBUS_BANK + 0x12)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_pm_sleep.h | 527 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
528 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
529 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
530 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
531 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
532 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
533 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
534 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
535 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
536 #define REG_MHL_CBUS_09 (REG_MHL_CBUS_BANK + 0x12)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_pm_sleep.h | 527 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
528 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
529 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
530 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
531 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
532 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
533 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
534 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
535 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
536 #define REG_MHL_CBUS_09 (REG_MHL_CBUS_BANK + 0x12)
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/ |
| H A D | hwregMHL.h | 110 #define REG_MHL_CBUS_BANK 0x001F00 macro
115 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
116 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
117 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
118 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
119 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
120 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
121 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
122 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
123 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/ |
| H A D | hwregMHL.h | 110 #define REG_MHL_CBUS_BANK 0x001F00 macro
115 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00)
116 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
117 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
118 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
119 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
120 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
121 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
122 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
123 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | hwreg_mhl.h | 92 #define REG_MHL_CBUS_BANK 0x001F00 macro
97 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
98 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
99 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
100 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
101 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
102 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
103 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
104 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
105 #define REG_MHL_CBUS_14 (REG_MHL_CBUS_BANK + 0x28)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | hwreg_mhl.h | 92 #define REG_MHL_CBUS_BANK 0x001F00 macro
97 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02)
98 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04)
99 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06)
100 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08)
101 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A)
102 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C)
103 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E)
104 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10)
105 #define REG_MHL_CBUS_14 (REG_MHL_CBUS_BANK + 0x28)
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | mhal_xc_chip_config.h | 470 #define REG_MHL_CBUS_BANK 0x001F00UL macro
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