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Searched refs:REG_IRQ_MASK_H (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c508 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
527 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
587 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
606 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
1644 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1663 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
1723 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1742 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h129 #define REG_IRQ_MASK_H 0x0035 macro
173 #define REG_IRQ_MASK_H (REG_INT_BASE_ADDR + 0x0015) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c508 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
527 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
587 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
606 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
1644 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1663 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
1723 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1742 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h129 #define REG_IRQ_MASK_H 0x0035 macro
173 #define REG_IRQ_MASK_H (REG_INT_BASE_ADDR + 0x0015) macro
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c508 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
527 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
587 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
606 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
1631 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1650 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
1710 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1729 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h129 #define REG_IRQ_MASK_H 0x0035 macro
173 #define REG_IRQ_MASK_H (REG_INT_BASE_ADDR + 0x0015) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c508 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
527 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
587 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
606 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
1644 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1663 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
1723 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1742 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h129 #define REG_IRQ_MASK_H 0x0035 macro
173 #define REG_IRQ_MASK_H (REG_INT_BASE_ADDR + 0x0015) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c508 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
527 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
587 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
606 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
1644 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
1663 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
1723 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
1742 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
H A DregCHIP.h129 #define REG_IRQ_MASK_H 0x0035 macro
173 #define REG_IRQ_MASK_H (REG_INT_BASE_ADDR + 0x0015) macro
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DhalCHIP.c440 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
454 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x1 << (u8VectorIndex-E_IRQH_START) ); in CHIP_EnableIRQ()
499 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
513 IRQ_REG(REG_IRQ_MASK_H) |= (0x1 << (u8VectorIndex-E_IRQH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h148 #define REG_IRQ_MASK_H 0x0035 macro
175 #define REG_IRQ_MASK_H 0x0035 macro
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DhalCHIP.c440 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
454 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x1 << (u8VectorIndex-E_IRQH_START) ); in CHIP_EnableIRQ()
499 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
513 IRQ_REG(REG_IRQ_MASK_H) |= (0x1 << (u8VectorIndex-E_IRQH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h148 #define REG_IRQ_MASK_H 0x0035 macro
173 #define REG_IRQ_MASK_H 0x0035 macro
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DhalCHIP.c440 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
454 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x1 << (u8VectorIndex-E_IRQH_START) ); in CHIP_EnableIRQ()
499 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
513 IRQ_REG(REG_IRQ_MASK_H) |= (0x1 << (u8VectorIndex-E_IRQH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h148 #define REG_IRQ_MASK_H 0x0035 macro
173 #define REG_IRQ_MASK_H 0x0035 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DhalCHIP.c423 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
437 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
481 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
495 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DhalCHIP.c440 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
454 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x1 << (u8VectorIndex-E_IRQH_START) ); in CHIP_EnableIRQ()
499 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
513 IRQ_REG(REG_IRQ_MASK_H) |= (0x1 << (u8VectorIndex-E_IRQH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h148 #define REG_IRQ_MASK_H 0x0035 macro
173 #define REG_IRQ_MASK_H 0x0035 macro
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DhalCHIP.c440 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
454 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x1 << (u8VectorIndex-E_IRQH_START) ); in CHIP_EnableIRQ()
499 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
513 IRQ_REG(REG_IRQ_MASK_H) |= (0x1 << (u8VectorIndex-E_IRQH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h148 #define REG_IRQ_MASK_H 0x0035 macro
173 #define REG_IRQ_MASK_H 0x0035 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DhalCHIP.c423 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
437 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
481 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
495 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DhalCHIP.c423 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
437 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_EnableIRQ()
481 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
495 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DhalCHIP.c440 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
454 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x1 << (u8VectorIndex-E_IRQH_START) ); in CHIP_EnableIRQ()
499 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF; in CHIP_DisableIRQ()
513 IRQ_REG(REG_IRQ_MASK_H) |= (0x1 << (u8VectorIndex-E_IRQH_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h148 #define REG_IRQ_MASK_H 0x0035 macro
175 #define REG_IRQ_MASK_H 0x0035 macro

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