Home
last modified time | relevance | path

Searched refs:REG_FIQ_MASK_L (Results 1 – 25 of 28) sorted by relevance

12

/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c511 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
547 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
590 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
626 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
1647 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1683 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
1726 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1762 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h115 #define REG_FIQ_MASK_L 0x0024 macro
142 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c511 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
547 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
590 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
626 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
1647 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1683 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
1726 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1762 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h115 #define REG_FIQ_MASK_L 0x0024 macro
142 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004) macro
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c511 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
547 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
590 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
626 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
1634 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1670 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
1713 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1749 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h115 #define REG_FIQ_MASK_L 0x0024 macro
142 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c511 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
547 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
590 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
626 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
1647 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1683 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
1726 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1762 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h115 #define REG_FIQ_MASK_L 0x0024 macro
142 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c511 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
547 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
590 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
626 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
1647 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
1683 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
1726 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
1762 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
H A DregCHIP.h115 #define REG_FIQ_MASK_L 0x0024 macro
142 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004) macro
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DhalCHIP.c443 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
466 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_EnableIRQ()
502 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
525 IRQ_REG(REG_FIQ_MASK_L) |= (0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h134 #define REG_FIQ_MASK_L 0x0024 macro
160 #define REG_FIQ_MASK_L 0x0024 macro
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DhalCHIP.c443 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
466 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_EnableIRQ()
502 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
525 IRQ_REG(REG_FIQ_MASK_L) |= (0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h134 #define REG_FIQ_MASK_L 0x0024 macro
159 #define REG_FIQ_MASK_L 0x0024 macro
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DhalCHIP.c443 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
466 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_EnableIRQ()
502 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
525 IRQ_REG(REG_FIQ_MASK_L) |= (0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h134 #define REG_FIQ_MASK_L 0x0024 macro
159 #define REG_FIQ_MASK_L 0x0024 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DhalCHIP.c426 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
449 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
484 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
507 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DhalCHIP.c443 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
466 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_EnableIRQ()
502 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
525 IRQ_REG(REG_FIQ_MASK_L) |= (0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h134 #define REG_FIQ_MASK_L 0x0024 macro
159 #define REG_FIQ_MASK_L 0x0024 macro
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DhalCHIP.c443 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
466 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_EnableIRQ()
502 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
525 IRQ_REG(REG_FIQ_MASK_L) |= (0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h134 #define REG_FIQ_MASK_L 0x0024 macro
159 #define REG_FIQ_MASK_L 0x0024 macro
/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DhalCHIP.c426 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
449 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
484 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
507 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DhalCHIP.c426 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
449 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_EnableIRQ()
484 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
507 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DhalCHIP.c443 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
466 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_EnableIRQ()
502 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF; in CHIP_DisableIRQ()
525 IRQ_REG(REG_FIQ_MASK_L) |= (0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_DisableIRQ()
H A DregCHIP.h134 #define REG_FIQ_MASK_L 0x0024 macro
160 #define REG_FIQ_MASK_L 0x0024 macro

12