| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_hdmi.c | 1199 …W2BYTEMSK(REG_DVI_DTOP_20_L, BIT(13)| ((HDMI_R_CHANNEL_EQ_VALUE << 8)| (HDMI_G_CHANNEL_EQ_VALUE <<… in Hal_HDMI_init()
1458 W2BYTEMSK(REG_DVI_DTOP_20_L+u16bank_offset, 0x0555, 0x0FFF); in Hal_HDMI_Set_EQ()
1461 W2BYTEMSK(REG_DVI_DTOP_20_L+u16bank_offset, 0x0AAA, 0x0FFF); in Hal_HDMI_Set_EQ()
1464 W2BYTEMSK(REG_DVI_DTOP_20_L+u16bank_offset, 0x0CCC, 0x0FFF); in Hal_HDMI_Set_EQ()
1467 W2BYTEMSK(REG_DVI_DTOP_20_L+u16bank_offset, 0xFFFF, 0x0FFF); in Hal_HDMI_Set_EQ()
1470 W2BYTEMSK(REG_DVI_DTOP_20_L+u16bank_offset, (temp)|(temp<<4)|(temp<<8), 0x0FFF); in Hal_HDMI_Set_EQ()
1473 W2BYTEMSK(REG_DVI_DTOP_20_L+u16bank_offset, 0x0AAA, 0x0FFF); in Hal_HDMI_Set_EQ()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_hdmi.c | 1199 …W2BYTEMSK(REG_DVI_DTOP_20_L, BIT(13)| ((HDMI_R_CHANNEL_EQ_VALUE << 8)| (HDMI_G_CHANNEL_EQ_VALUE <<… in Hal_HDMI_init()
1458 W2BYTEMSK(REG_DVI_DTOP_20_L+u16bank_offset, 0x0555, 0x0FFF); in Hal_HDMI_Set_EQ()
1461 W2BYTEMSK(REG_DVI_DTOP_20_L+u16bank_offset, 0x0AAA, 0x0FFF); in Hal_HDMI_Set_EQ()
1464 W2BYTEMSK(REG_DVI_DTOP_20_L+u16bank_offset, 0x0CCC, 0x0FFF); in Hal_HDMI_Set_EQ()
1467 W2BYTEMSK(REG_DVI_DTOP_20_L+u16bank_offset, 0xFFFF, 0x0FFF); in Hal_HDMI_Set_EQ()
1470 W2BYTEMSK(REG_DVI_DTOP_20_L+u16bank_offset, (temp)|(temp<<4)|(temp<<8), 0x0FFF); in Hal_HDMI_Set_EQ()
1473 W2BYTEMSK(REG_DVI_DTOP_20_L+u16bank_offset, 0x0AAA, 0x0FFF); in Hal_HDMI_Set_EQ()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/ |
| H A D | halMHL.c | 398 W2BYTEMSK(REG_DVI_DTOP_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_HdmiBypassModeSetting()
528 W2BYTEMSK(REG_DVI_DTOP_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_Mhl24bitsModeSetting()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/ |
| H A D | halMHL.c | 398 W2BYTEMSK(REG_DVI_DTOP_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_HdmiBypassModeSetting()
528 W2BYTEMSK(REG_DVI_DTOP_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength in _mhal_mhl_Mhl24bitsModeSetting()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 4441 … W2BYTEMSK( REG_DVI_DTOP_20_L+u16bank_offset, 0x0CCF, 0x0FFF); // B_CH = 0xF, G and R_CH = 0xC in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 4379 … W2BYTEMSK( REG_DVI_DTOP_20_L+u16bank_offset, 0x0CCF, 0x0FFF); // B_CH = 0xF, G and R_CH = 0xC in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 4441 … W2BYTEMSK( REG_DVI_DTOP_20_L+u16bank_offset, 0x0CCF, 0x0FFF); // B_CH = 0xF, G and R_CH = 0xC in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 4581 … W2BYTEMSK( REG_DVI_DTOP_20_L+u16bank_offset, 0x0CCF, 0x0FFF); // B_CH = 0xF, G and R_CH = 0xC in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 4581 … W2BYTEMSK( REG_DVI_DTOP_20_L+u16bank_offset, 0x0CCF, 0x0FFF); // B_CH = 0xF, G and R_CH = 0xC in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_hdmi.h | 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) macro
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