| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/ |
| H A D | halMHL.c | 269 W2BYTEMSK(REG_DVI_DTOP_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
274 W2BYTEMSK(REG_DVI_DTOP_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/ |
| H A D | halMHL.c | 269 W2BYTEMSK(REG_DVI_DTOP_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
274 W2BYTEMSK(REG_DVI_DTOP_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 4453 … MDrv_WriteByteMask(REG_DVI_DTOP_00_L+u16bank_offset, BIT(4), BIT(4)); // enable EQ new mode in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 4391 … MDrv_WriteByteMask(REG_DVI_DTOP_00_L+u16bank_offset, BIT(4), BIT(4)); // enable EQ new mode in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 4453 … MDrv_WriteByteMask(REG_DVI_DTOP_00_L+u16bank_offset, BIT(4), BIT(4)); // enable EQ new mode in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 4593 … MDrv_WriteByteMask(REG_DVI_DTOP_00_L+u16bank_offset, BIT(4), BIT(4)); // enable EQ new mode in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 4593 … MDrv_WriteByteMask(REG_DVI_DTOP_00_L+u16bank_offset, BIT(4), BIT(4)); // enable EQ new mode in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_hdmi.h | 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) macro
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