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Searched refs:REG_DVI_ATOP_06_L (Results 1 – 25 of 53) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_mux.c374 W2BYTEMSK(REG_DVI_ATOP_06_L, 0, 0xFFFF); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
387 W2BYTE(REG_DVI_ATOP_06_L, 0); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
407 … W2BYTEMSK(REG_DVI_ATOP_06_L, 0x6F7E, 0x7FFE); // disable DVI0 clock power, bit[7]=0 audio clock in Hal_SC_mux_set_dvi_mux()
420 … W2BYTEMSK(REG_DVI_ATOP_06_L, 0xEF7E, 0xFFFE); // disable DVI0 clock power, bit[7]=0 audio clock in Hal_SC_mux_set_dvi_mux()
440 … W2BYTEMSK(REG_DVI_ATOP_06_L, 0x6F7E, 0x7FFE); // disable DVI0 clock power, bit[7]=0 audio clock in Hal_SC_mux_set_dvi_mux()
453 … W2BYTEMSK(REG_DVI_ATOP_06_L, 0xEF7E, 0xFFFE); // disable DVI0 clock power, bit[7]=0 audio clock in Hal_SC_mux_set_dvi_mux()
473 … W2BYTEMSK(REG_DVI_ATOP_06_L, 0x6F7E, 0x7FFE); // disable DVI0 clock power, bit[7]=0 audio clock in Hal_SC_mux_set_dvi_mux()
486 … W2BYTEMSK(REG_DVI_ATOP_06_L, 0xEF7E, 0xFFFE); // disable DVI0 clock power, bit[7]=0 audio clock in Hal_SC_mux_set_dvi_mux()
506 W2BYTEMSK(REG_DVI_ATOP_06_L, 0x7FFE, 0x7FFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
519 W2BYTEMSK(REG_DVI_ATOP_06_L, 0xFFFE, 0xFFFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
H A Dmhal_offline.c361 MS_U16 u16DVIATOP_06 = R2BYTE(REG_DVI_ATOP_06_L); in Hal_XC_GetOffLineOfDVI0()
365 W2BYTE(REG_DVI_ATOP_06_L, 0); // enable DVI0 clock power in Hal_XC_GetOffLineOfDVI0()
382 W2BYTE(REG_DVI_ATOP_06_L, u16DVIATOP_06); in Hal_XC_GetOffLineOfDVI0()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_mux.c374 W2BYTEMSK(REG_DVI_ATOP_06_L, 0, 0xFFFF); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
387 W2BYTE(REG_DVI_ATOP_06_L, 0); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
407 … W2BYTEMSK(REG_DVI_ATOP_06_L, 0x6F7E, 0x7FFE); // disable DVI0 clock power, bit[7]=0 audio clock in Hal_SC_mux_set_dvi_mux()
420 … W2BYTEMSK(REG_DVI_ATOP_06_L, 0xEF7E, 0xFFFE); // disable DVI0 clock power, bit[7]=0 audio clock in Hal_SC_mux_set_dvi_mux()
440 … W2BYTEMSK(REG_DVI_ATOP_06_L, 0x6F7E, 0x7FFE); // disable DVI0 clock power, bit[7]=0 audio clock in Hal_SC_mux_set_dvi_mux()
453 … W2BYTEMSK(REG_DVI_ATOP_06_L, 0xEF7E, 0xFFFE); // disable DVI0 clock power, bit[7]=0 audio clock in Hal_SC_mux_set_dvi_mux()
473 … W2BYTEMSK(REG_DVI_ATOP_06_L, 0x6F7E, 0x7FFE); // disable DVI0 clock power, bit[7]=0 audio clock in Hal_SC_mux_set_dvi_mux()
486 … W2BYTEMSK(REG_DVI_ATOP_06_L, 0xEF7E, 0xFFFE); // disable DVI0 clock power, bit[7]=0 audio clock in Hal_SC_mux_set_dvi_mux()
506 W2BYTEMSK(REG_DVI_ATOP_06_L, 0x7FFE, 0x7FFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
519 W2BYTEMSK(REG_DVI_ATOP_06_L, 0xFFFE, 0xFFFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
H A Dmhal_offline.c361 MS_U16 u16DVIATOP_06 = R2BYTE(REG_DVI_ATOP_06_L); in Hal_XC_GetOffLineOfDVI0()
365 W2BYTE(REG_DVI_ATOP_06_L, 0); // enable DVI0 clock power in Hal_XC_GetOffLineOfDVI0()
382 W2BYTE(REG_DVI_ATOP_06_L, u16DVIATOP_06); in Hal_XC_GetOffLineOfDVI0()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/cec/
H A Dmhal_cec.c405 MDrv_WriteByte( REG_DVI_ATOP_06_L, MDrv_ReadByte(REG_DVI_ATOP_06_L) &(~ BIT(0))); in mhal_CEC_ConfigWakeUp()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/cec/
H A Dmhal_cec.c405 MDrv_WriteByte( REG_DVI_ATOP_06_L, MDrv_ReadByte(REG_DVI_ATOP_06_L) &(~ BIT(0))); in mhal_CEC_ConfigWakeUp()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/cec/include/
H A Dcec_hwreg.h139 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/cec/include/
H A Dcec_hwreg.h139 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/cec/include/
H A Dcec_hwreg.h142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_dvi_atop.h114 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_dvi_atop.h114 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_dvi_atop.h114 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_dvi_atop.h114 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) macro

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